Intel iBooks in March? Media Center and Cell Phone Rumblings

[gnasher729]

I don't like the idea of having a DVR. It might be cool for you folks in the US who tend to use Cable which you can use the normal tuners in TVs or TV cards but over here in the UK we use satellite (Sky) way more than cable and the tuners are built into the decoder/receiver box supplied by Sky. An HD DVR that isn't supplied by Sky just wouldn't cut it. A Tivo connected to Sky can only ever access the channel Sky's plugged into and that's one channel at a time.

A harddisk recorder with two Freeview tuners works just fine. No monthly fee, no extra fee of any kind, plenty of channels, good picture quality.

Well, Apple has been releasing G4 and G5 processors that are faster than anything Moto or IBM claim to ship.

Maybe it's just overclocking - maybe IBM and Moto have been doing something special for The Steve.

Here is how it worked on the Motorola side: Motorola built the chips in three variations: Normal, Low Power and Extremely Low Power. Only one customer for the "Normal" variant, and that is Apple. As a result, the "Normal" chips don't turn up in any Motorola price list. And the lower power chips run slower. Therefore, Apple always had chips that were faster than anything in the Motorola price list, but they were regular Motorola chips, used within their specification and tested by Motorola to run at that speed.

 

[Xgreed]

iPod Phone presented

the iPod Phone has been presented.
I is available in the classic white as well as in black as all recent members of the iPod line.

More information available here:http://www.sonyericsson.com/spg.jsp...oader&php=php1_10385&zone=pp&lm=pp1&pid=10385
Good work Apple, err. SonyEricsson!

 

[bruf]

MacBook specs

Hi,

First post here. I've read a lot of posts lately on macrumors and many people seem to have somewhat low expectations for the MacBook / iBook replacements. I agree that you cannot compare side-by-side a Mac laptop to a PC laptop from the folks @ Dell or Acer on a pricing standpoint, primarly because of the OS and the software that's included with the new Macs. But in the end for Apple, the profit/margin they do on all their products is pretty high, even when you consider the promo and branding these products benefit from. It's even higher when you only consider the hardware parts they put in it, which aren't top-of-the-line imho, even in the MBPs.

Because of that, I expect a lot from Apple for the new MacBook/iBook revision. I hope we'll have something like :

- 1.67 Intel Core Solo
- 512MB DDR2 RAM
- 13.3" & 15.4" display options
- ATI Mobility Radeon X1300 w/64MB
- Dual display and video mirroring support
- DVI output
- 40/60GB 5400-rpm Serial ATA hard drive
- Built-in iSight camera
+ all the usual (USB2, FW400, Airport, BT2.0+EDR)

I don't expect to have advanced features like optical/analog audio, backlit keyboard or even a modem, but I do hope that Apple will be using Serial ATA storage and PCI-Ex for video instead of old technologies in the actual iBooks.

Am I a little too optimistic here?

Take care,

Bruno

 

[chemtw]

Enough Talk, im tired of waiting, I just wanna see the thing. Come on apple gimme gimme please!!

Hi,

First post here. I've read a lot of posts lately on macrumors and many people seem to have somewhat low expectations for the MacBook / iBook replacements. I agree that you cannot compare side-by-side a Mac laptop to a PC laptop from the folks @ Dell or Acer on a pricing standpoint, primarly because of the OS and the software that's included with the new Macs. But in the end for Apple, the profit/margin they do on all their products is pretty high, even when you consider the promo and branding these products benefit from. It's even higher when you only consider the hardware parts they put in it, which aren't top-of-the-line imho, even in the MBPs.

Because of that, I expect a lot from Apple for the new MacBook/iBook revision. I hope we'll have something like :

- 1.67 Intel Core Solo
- 512MB DDR2 RAM
- 13.3" & 15.4" display options
- ATI Mobility Radeon X1300 w/64MB
- Dual display and video mirroring support
- DVI output
- 40/60GB 5400-rpm Serial ATA hard drive
- Built-in iSight camera
+ all the usual (USB2, FW400, Airport, BT2.0+EDR)

I don't expect to have advanced features like optical/analog audio, backlit keyboard or even a modem, but I do hope that Apple will be using Serial ATA storage and PCI-Ex for video instead of old technologies in the actual iBooks.

Am I a little too optimistic here?

Take care,

Bruno

 

[mi5moav]

Yes, I would have to second that motion. But it was quite a waste of time.

 

[Meemoo]

It'd be stupid for Apple to not release a MacBook Pro thats 12/13 inches with a core duo. I'd pay the going rate, but to make me buy bigger when perhaps I need a bit more portability?

 

[dialectician]

Any chance of a light-weight ibook/mac book w/o drive?

Hi there.

Any chance Apple will release a light-weight ibook/mac book without an optical drive or with a docking station? I am sick and tired of carrying 6 pounds of tech-junk around with me every day. How come IBM, Sony, Toshiba and Dell have all released tiny and light laptops years ago and Apple still hasn't?

 

[chemtw]

Cause its easier to produce junk
Whereas apple actually works at creating quality
but actually Im with you I want my light weight apple laptop

Hi there.

Any chance Apple will release a light-weight ibook/mac book without an optical drive or with a docking station? I am sick and tired of carrying 6 pounds of tech-junk around with me every day. How come IBM, Sony, Toshiba and Dell have all released tiny and light laptops years ago and Apple still hasn't?

 

[AidenShaw]

BS alert

None of us are sure how much footprint the Rosetta related data is going to take up at the CPU Cache level, but the P-M architecture is optimized for quick L2 access to compensate the lagging FSB, and the Intel engineers have decided that between 2MB to 4MB is the sweet spot that will fit most program's instructions on core while executing. If you are emulating, the emulation layer has to be kept on die for fast access, as well as the program you are going to be emulating, and therefore, 2MB is the lower estimate for how much it is going to be needing if the emulated programs are small and rosetta is efficient. 4MB almost sounds essential for non-optimized programs and treating Rosetta as any other program per Intel's estimates.

The "sweet spot" is as much cache as they can realistically and economically fit onto the chip, that's been the case since day 1.

"the emulation layer has to be kept on die" - nonsense. QuickTransit is a translator, once a code stream has been translated (into main memory, by the way) the translator isn't involved and doesn't have to be in cache. Depending on the application, other parts of QuickTransit may or may not be needed. (Note that since Rosetta is OSX.ppc -> OSX.x86 - the emulation of the operating system calls is very easy and lightweight.)

The "sweet spot" with cache has to do with the hit/miss ratio. You'll almost never be able to keep everything in cache, so the point is to have a high enough hit ratio that performance is more or less the same as a 100% hit ratio.

That spot is very program dependent (even without QuickTransit in the picture), and includes both instructions and data.

I await your benchmarks which show that Rosetta performance suffers greatly when cache is reduced below 2 MiB....

Or at least provide a link from Transitive engineering which supports your claims about cache sizes.

 

[Maxx Power]

The "sweet spot" is as much cache as they can realistically and economically fit onto the chip, that's been the case since day 1.

"the emulation layer has to be kept on die" - nonsense. QuickTransit is a translator, once a code stream has been translated (into main memory, by the way) the translator isn't involved and doesn't have to be in cache. Depending on the application, other parts of QuickTransit may or may not be needed. (Note that since Rosetta is OSX.ppc -> OSX.x86 - the emulation of the operating system calls is very easy and lightweight.)

The "sweet spot" with cache has to do with the hit/miss ratio. You'll almost never be able to keep everything in cache, so the point is to have a high enough hit ratio that performance is more or less the same as a 100% hit ratio.

That spot is very program dependent (even without QuickTransit in the picture), and includes both instructions and data.

I await your benchmarks which show that Rosetta performance suffers greatly when cache is reduced below 2 MiB....

Or at least provide a link from Transitive engineering which supports your claims about cache sizes.

I never made any claims about Transitive engineering. I sais that per intel engineering team design, the L2 cache of the P-M series of chips is where the common code speed up comes from when executed on P-M. They predicted that 2MB would be sufficient to provide a greater than 90% hit rate when executing optimized code on standard sized X86 programs. Therefore, I was concluding, that including some instructions and data from the emulation layer Rosetta, there must be a total of more than 2MB cache to be able to execute the program with as much hit rate in L2 cache. Remember, the PM has a lousy access latency to the main memory, if the translated code plus whatever else the CPU needs access to can't be fitted inside the L2, the IPC drops drastically since the CPU has to wait for the FSB latency cycles.

 

[AidenShaw]

You have no basis for your conclusions...

I never made any claims about Transitive engineering. I sais that per intel engineering team design, the L2 cache of the P-M series of chips is where the common code speed up comes from when executed on P-M. They predicted that 2MB would be sufficient to provide a greater than 90% hit rate when executing optimized code on standard sized X86 programs. Therefore, I was concluding, that including some instructions and data from the emulation layer Rosetta, there must be a total of more than 2MB cache to be able to execute the program with as much hit rate in L2 cache. Remember, the PM has a lousy access latency to the main memory, if the translated code plus whatever else the CPU needs access to can't be fitted inside the L2, the IPC drops drastically since the CPU has to wait for the FSB latency cycles.

Please post a link to the "intel engineering team design" documents....

Think about this....

I'm running QuickTransit on Photoshop, with a 500 MB PSD file. Since my filter has to run through 500 MB of data (probably much larger when converted to in-memory format), and convert it to a different in-memory image of at least the same size, and maybe has to run through it multiple times - how can you ad hoc claim that 1 MiB cache is too little, and 2 MiB cache will be fine?

The cache is far, far smaller than the data....

Please, the links to engineering reports on the efficacy of cache for this application...

(p.s. I've used Celerons for extended times in several systems. My conclusion is that careful tests will show that they're a bit slower than the "high-priced chip" of the same clock rate - but that most people won't ever see the difference. IMO most of the "Celerons suck" and "Celerons will suck at Rosetta" posts are naïve conclusions from people who don't understand the difference between what the spec sheet for a chip says, and what a *system* delivers to the user. A 2X difference on the spec sheet is often almost impossible for the user to distinguish.)

(p.p.s. Digital once shipped an Alpha system for servers with the option of *no* L2 cache whatsoever. On many file sharing and network server benchmarks - the "cacheless" system was faster than the system with 2 MiB of L2. The reason was simple and obvious. A file server is sending huge amounts of data through the system - and never touching the same byte twice. The cache introduced a couple of extra cycles of latency - therefore the system never recovered those extra cycles because the data was never reused. The tight instruction loops for the serving fit in the L1 instruction cache, so no problem there.

Sometimes naïve people claim that "more is better", when in fact "none is best".)

(p.p.p.s. Please note that I'm not saying that you aren't correct - but you have yet to back up any of your claims with independent articles about QuickTransit. I would expect QuickTransit would be faster with larger cache, but I won't buy "QuickTransit will suck with 1 MiB and fly with 2 MiB" without some real-life benchmark data on how QT runs with multiple applications on different systems with different amounts of cache. If it's a few percent faster with 2 MiB, who cares? If it's 50% faster - give me a ticket to the "Celeron Sucks" cheering section and a pair of pink and fuschia feathered Pom-Poms!)

 

[themacman]

Im more curious as to what the new iBook(MacBook?) enclosures are gonna look like...

yah. a change to the ibook enclosure to somethign really cool could really make this a great seller.

 

[Maxx Power]

Please post a link to the "intel engineering team design" documents....

Think about this....

I'm running QuickTransit on Photoshop, with a 500 MB PSD file. Since my filter has to run through 500 MB of data (probably much larger when converted to in-memory format), and convert it to a different in-memory image of at least the same size, and maybe has to run through it multiple times - how can you ad hoc claim that 1 MiB cache is too little, and 2 MiB cache will be fine?

The cache is far, far smaller than the data....

Please, the links to engineering reports on the efficacy of cache for this application...

(p.s. I've used Celerons for extended times in several systems. My conclusion is that careful tests will show that they're a bit slower than the "high-priced chip" of the same clock rate - but that most people won't ever see the difference. IMO most of the "Celerons suck" and "Celerons will suck at Rosetta" posts are naïve conclusions from people who don't understand the difference between what the spec sheet for a chip says, and what a *system* delivers to the user. A 2X difference on the spec sheet is often almost impossible for the user to distinguish.)

(p.p.s. Digital once shipped an Alpha system for servers with the option of *no* L2 cache whatsoever. On many file sharing and network server benchmarks - the "cacheless" system was faster than the system with 2 MiB of L2. The reason was simple and obvious. A file server is sending huge amounts of data through the system - and never touching the same byte twice. The cache introduced a couple of extra cycles of latency - therefore the system never recovered those extra cycles because the data was never reused. The tight instruction loops for the serving fit in the L1 instruction cache, so no problem there.

Sometimes naïve people claim that "more is better", when in fact "none is best".)

(p.p.p.s. Please note that I'm not saying that you aren't correct - but you have yet to back up any of your claims with independent articles about QuickTransit. I would expect QuickTransit would be faster with larger cache, but I won't buy "QuickTransit will suck with 1 MiB and fly with 2 MiB" without some real-life benchmark data on how QT runs with multiple applications on different systems with different amounts of cache. If it's a few percent faster with 2 MiB, who cares? If it's 50% faster - give me a ticket to the "Celeron Sucks" cheering section and a pair of pink and fuschia feathered Pom-Poms!)

I have to refer you to Arstechnica.com, they have an archive of CPU articles.

for L2 Importance, refer to:
http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2342&p=5
With the recent price cuts on Pentium M, and the fact you can't get celeron models at high speed as the P-M models, it is a worthwhile processor for the budget if apple is going for 1.7Ghz and above.

http://www.anandtech.com/printarticle.aspx?i=2129
"ICC SYSMark 2004 has always favored Intel processors; more specifically, the Pentium 4. Under the older SYSMark 2002 benchmark, this was the only test where the Pentium M could not hang with its older brother. This time around, we see that the Banias based Pentium M doesn't fair well at all, but with a few architectural tweaks, twice the cache and a higher clock speed, the Pentium M 755 is nipping at the heels of the Pentium 4."

Also, there are 512KB celerons:
http://balusc.xs4all.nl/srv/har-cpu-int-pm.php

 

[AidenShaw]

I have to refer you to Arstechnica.com, they have an archive of CPU articles.

for L2 Importance, refer to:
http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2342&p=5
http://www.anandtech.com/printarticle.aspx?i=2129
http://balusc.xs4all.nl/srv/har-cpu-int-pm.php

All interesting, but where in any of these articles is QuickTransit mentioned?

This tangent is about the claim that a smaller cache chip isn't viable because Rosetta needs more cache than native applications.

I've been asking for that claim to be supported, not a bunch of benchmarks that say that native Windows apps run faster with larger cache.

 

[Maxx Power]

All interesting, but where in any of these articles is QuickTransit mentioned?

This tangent is about the claim that a smaller cache chip isn't viable because Rosetta needs more cache than native applications.

I've been asking for that claim to be supported, not a bunch of benchmarks that say that native Windows apps run faster with larger cache.

What's the difference ? I suggested that Rosetta MAY need more cache space in which case, more cache is beneficial, to the point of not overdoing it. Say you have no loss in using the QuickTransit method, the applications would still end up being faster with a Dothan. With losses, the loss will be the same on Dothan as Celeron-M if it fits in the cache, and more so on the Celeron-M if not. either way my speculation remains valid. It may not amount to more than 5 - 10% if the code fits inside the L2, but if the code is in between 1 and 2MB then the Dothan will have a big advantage. Any of these scenarios point to what I have already said. I'm not suggesting "More is better" or "if it feels good, do it" like some people with these western attitudes. I will pay the extra 100 dollars for double L2 and speedstep with deep sleep on a Dothan based book, but not 1000 dollars more for 4 times the cache, this is in no way "More is better", it's optimizations. It's just my theory, either way, we'll find out when the iBooks come out and we can compare it to the MacBook Pro's.

BTW, did you miss the benchmark a few days ago of UT2004 running under Rosetta on the new iMac, 8fps, obviously the translation method is inefficient at least for this game and any other game based on the UT engine. Some other games ran fine though, a little slower, but good enough.

Oh, and also just found this "I just tried Photoshop under Rosetta at the Applestore in Willow Bend.
It was slow as molass trying to run some filters on a large JPEG.
Everything else more or less flew but for heavy applications like PS under Rosetta you have to have some patience. It was slower than my current imac 800MHz G4..."
https://forums.macrumors.com/threads/175030/
Rosetta is also slow for some filters as well.

 

[AidenShaw]

I suggested that Rosetta MAY need more cache space in which case, more cache is beneficial, to the point of not overdoing it.

Fair enough - as long as cache is discussed in general terms, and not the specific claims made in post #138.

 

[Maxx Power]

Fair enough - as long as cache is discussed in general terms, and not the specific claims made in post #138.

Those specific claims were case scenarios using 2MB as engineer assumptions for good performance and if Rosetta requires any memory space and/or the translated instructions greater than or equals to the length of untranslated codes.

Give it a few more weeks, I figure the iBooks'll be out then, At the current price points, I think Apple can stick in a good processor.

 

[stefan15]

It had better be a Core DUO. It would be senseless to include a core solo and I'm not even sure why it's even being released. Intel's roadmap include 8 cores in 2008. 4 Cores in 2007. Single core is already a way of the past, why not move forward.

By way of caches... Intel just annouced it's new server processor including a 16mb unified cache for smoother virtualization. 16mb!

 

[ScottB]

It had better be a Core DUO.

I'll second that. I'll still be pleased with a core solo, simply because It'll last me a lot longer (in terms of software updates) than any G4 laptop. And boy, I do not buy computers often (new iBook will be my second computer!). But, to be honest I'll be very disappointed and it'll undermine the whole reason I buy Apple products. I recommend macintosh computers to people who ask because I'm sure they'll get their money worth, but with core solo's it'll be alot harder to convince people this, if not myself, because I'll feel the notebook is purposely downgraded so to not come close to the MacBook Pro (even if this is not the case). I don't know much about hardware, so take advantage of that... shove in a duo and not a solo and I'll be gullible enough to be impressed. Alternatively you could ram in a whole load of fancy consumer gadgets (common iSight! and oh god give me that bionic thing thinkpads have!).

 

[Val-kyrie]

I would like to see them stick with two models, maybe a 13.3" and 15.4" in Black or White. I certainly wouldn't believe a single MacBook, (I'm ditching the express suffix as it seems less likely by the day), would be a wise move as consumers want choice. I would like to see something like:

13.3" Core Solo 1.67GHz, 512MB, 60GB, 32MB x300 Graphics
15.4" Core Solo 1.83GHz, 512MB, 80GB, 64MB x300 Graphics

I hope you mean x1300, at least. Even the new Inspirons are set to be released with x1400 gfx cards.

Yeah, but at least you get a word processing software with a PC. Not even Appleworks is included anymore. And dont' give me the bull**** that "Textedit" is a good wordprocessor. Microsoft works, word, wordperfect, SOMETHING should be on the new iMacs so people don't HAVE to go out and buy MS Office. I bet that was the deal Apple made with MS to get them to agree to the new 5 year deal.

I have also heard good things about Mellel as a word processor. It is supposed to work well with BookEnds (for anyone needing a bibliographic program). Nisus Writer is another option. A comparison of three free and open source word processors may be found here. I can't boast any experience with any of them, but they are worth a look.

 

[Joe2000]

iBook (MacBook) Whatever...

I've got iWork 05' on my iMac and iBook and i think Pages is better than MS Word, Apple should include iWork and iLife in their new machines.

Does anyone have any idea how much the new intel iBook, MacBook whatever will cost?

- Joe.

 

[stefan15]

Speculate around USD1100?

Hopefully not a core solo, even the imac doesn't have that. It would definitely be a step backward. I'm surprised any manufacturer is releasing new models without a dual core processor. It's a way of the past. Isn't Apple supposed to be innovative?

 

[Mal]

Nah, they almost have to keep a $999 model around. Probably $999 and $1299, 13.3" both or a 13.3" and a 15.4". I wish there was a likelihood of a cheaper model, but I'm really doubting that. At least maybe the education discount will be better than current iBooks ($949 for iBook? What kinda crap is that?)

jW