Why Intel is so confident that they will gain "process performance leadership by 2025”? It is far behind TSMC and Samsung at present, and 2025 is not that far away. Did it get an endorsement from a superpower, say, NSA?
Intel has lots of money. They are getting the first NA-EUV fabrication machine from ASML. (so probably paying to be at the front of the line). There is no way TSMC or Samsung to bet them to NA-EUV pathfinding. If Intel blows their time on the "wrong" paths then eventually ASML will sell machines to the other two.
I suspect that has a better chance of being. "leading at lower volumes " (which is fine for more than a few Fab clients. Not Apple, but folks with higher priced silicon to sell ). Intel will probably never catch up on EUV fab capacity. But the next generation EUV tech starts out on roughly an even playing field again. That inflection point is an "in" for Intel. ( the previous two Intel CEO bonehead missed the EUV inflection point importance. )
Intel got an "endorsement" from. Qualcomm to put one product (not their entire line up) onto Intel's 20A . There is a chance Qualcomm is placing a bet in case. Samsung "gate all round" doesn't work out and TSMC can't do the volumes Qualcomm expects. In Monday's, Q&A after the presentation Intel mentioned that Qualcomm could be taking a "known" design and doing a shrink to Intel's 20A. So Intel could get a "tick-tock" progression but doesn't have to do both "halves" ( process shrink and new microarchitecture). That should help fab process go faster. If Intel foundry can find a client who wants to be on bleeding edge with a 50-80% smaller die than Intel's mainstream products then they can iterate on fab improvements without waiting around for the CPU package team to finish a large design.
That Intel 20A process could be 100% skipped by the CPU package folks if there is enough outside foundry customers to keep the EUV machines busy on EUV-20A mode. Intel takes all that learning and some very good NA-EUV path finding and applies that to 18A. That could end up largely closing the gap if there are no hiccups.
Intel has had several hiccups due to :
1. Only one primary customer (CPU packages) and a couple of "hostages" products ( Altera FGPA and modems made to use the process optimized for the CPUs. ).
2. Throwing out "tick tock" mindset (e.g,. manage the complexity by limiting things change at one time). The original stab at 10nm was trying to do a huge leap in one jump. Changed density , metal mixtures , patterning, and about 4-5 other things all at the same time. A series of yearly process of smaller jumps is simpler to manage the complexity due to less adverse interaction impacts.
3. "Premature optimization is the root of all evil " -- Knuth.
Intel doesn't have to be first on every dimension as soon as possible. They aren't shooting for most dense at any cost. The metric that they mentioned as their new baseline is Perf/watt. That means their wattage consumption may not be as low but if they get a bigger "bang for the buck" performance wise, then they'll take it.
A broader set of customers should help
1. Intel find a customer whose problem fits the fab process they do have working for now. For that customer they are a bleeding edge option.
2. if offer broader set of fab processes not all of them have to take larger leaps or get stuck.
( e.g., vaccine approach in 2020 in USA. Bet on 5 different vacinnes... at least one is a winner. Have to spend more to place more bets , but likelihood that they all loose goes down if try more concurrent options. Intel stop stock buy backs and invest in better fab process they could probably do alot if don't waste that amount of money. All the while 10nm was sucking wind , Intel was buying back billions. Get off of being 'stuck on stupid' and not surprising what can do. )
3. Spread the risk around to a broader set of libraries. Intel also mentions that they were going to try their "backside power deliver" on. Intel 4 or3 in a limited way before it was mainstream on Intel 20A. That again may be either a limited set of customer libraries or a limited subset of an intel design. Work out the kinks at a larger size and then roll it out at a smaller size on a broader scale.
"Make it work and then make it fast". There is not good reason to try all the new fab improvements in all of the libraries at the same time.
It won't be surprising if they end up with a fab process that isn't optimized for mobile products. Or if the fab biz lands a large enough mobile one then one of the alternatives is tweaked that way while the rest of the product line is on another with a different focus. ( If Intel has alternatives I doubt every single alternative will be bleeding edge best for every single market. )
Intel has historically got up and over promised. They may be over promising here too. But there is a difference this time in focus and risk mitigation. There are betting on some new major leaps. That their "gate all around" RibbonFET are more competitive. that they master the backside power delivery (Power Via) . That they work out all the kinks on EUV scale fabrication by the 3nd generation ( introduced at Intel 4 for several layers. More layers added at Intel 3 ) .
I would wager that in part they are pointing to "at risk" , early access to Intel 18A ( where they start up on NA-EUV) where they are talking parity more so than in extremely large scale production. That would be 2024 or so on their timeline. (but volume likely substantively later ).
