Intel Unveils 'Purley' Xeon Chip Lineup, but None are Appropriate for High-End iMac Pro

[hishnash]

the iMac Pro foresee 4 TBv3 ports, each requires 2-4 PCIe3 lines (8-16 max), a GPU requires 16 PCIe3 Lines, each NVMe SSD requires 4 PCIe3 Lines (8 More) as the 10Gbt Lan (4 PCIe3) other peripheral requires 3 more (USB3/WiFi/webcam) Required by an Maxed Out iMAc Pro are 16(GPU)+8(SSD)+[8/16(TBv3)+4(Lan)+3(Wifi/Usb3.1/etc)] total:24+15/23 intel X299 PCH (bassin fals) provides itself 24 PCIe3 lines, and Skylake-X HEDT HCC cpus provide 28-44PCIe3 lines, so the iMac Pro has enough PCIe lines (Lan, WiFi USB TBv3 and suport peripherals use to be wired to the PCH exclusively, that means the CPU only need to wire 24 of its minimal 28PCIe Lines in case they decide to wire each TBv3).

But what would the point be, it would still need to cost more than the iMAC and less than the iMAC pro and realy there is no space in the price range between the i7 iMac and the Xeon iMac pro. I don't see apple making a 5k -> 8k i9 powered iMac, (remember the x299 chipset and motherboards are just as costly to make as the Xeon boards)

If Apple dropped the price of the normal i7 iMac to 3k then maybe there would a be a price point for an i9 at 4k and 5k for a 8 and 10 core parts respectively. (since they would not have the costly ECC memory etc and would start with hybrid drivers rather than NVMe/(PCIe SSD). But that would push the i5 iMAC to under the price of a 5k p3 display...

Or of course apple could charge more of the iMAC Pro start it at 8k then there would be space but what is the point of that if they can provide you with the pro machine. (its not like they will OC the memory on the i9 your not going to end up with a much faster system)

When it comes to the macPro were they dont have the min price point (enforced by the display to consider) i could see a possibility for Apple to produce multiple main boards (though unlikely)

* an (i7/R7) board (a mac mini style machine with more of a pro focus)
* an (x299/x399) board (a macPro machine for users that dont need the validated memory and high core counts) it is looking like unless apple include an all-in-one water loop this will max out at 10 or 12 cores (for i9) given getting boost speeds on the 10core at the moment without an all-in-one is hard, its possible the 18core is much lower clock speed through.
* an (Xeon SP/Epyc) board (single socket) a real pro machine for those that need the validate memory and high core counts
* an 2P (Xeon SP/Epyc) board for realy high core counts and lots of IO/memory.

 

[Mago]

I don't see apple making a 5k -> 8k i9 powered iMac

I never said Apple Making an i9 Mac, what I was explaining is Intel is reading a Xeon Version of the i9 (with ECC and same X299 Chipset) it will be the iMac Pro's cpu (a xeon version from current i9).

Check the Xeon specification in the iMac Pro matches perfecty with i9 Bassin Fals, its well know Intel has pending a Xeon cpu for Workstations a different line from latest Server grade bronze/silver/gold-Xeon.

Even current X299 motherboard will support these xeon (confirmed by a friend) its ECC rm support wasn't announced yet as Intel and MB mfr want to deplete X99 and E5v4 Xeons.

 

[kiwipeso1]

Did you see the benchmarks Anandtech http://www.anandtech.com/show/11544/intel-skylake-ep-vs-amd-epyc-7000-cpu-battle-of-the-decade the AMD Epyic (4000$ parts) is beating the next gen intel (8000$) in many of the benchmarks and beating the Broadwell in all.

True AMD do not have the single thread integer performance but in floating point they beat intel even though they have a smaller vector width.

> without compromises like a x64 processor to execute native code
As far as we know apple don't have the patients to produce a chip like this without endless lawsuits.
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But it would require Apple to build a different board and at what price point would the i9 be?

it would need to cost more than the current i7 iMAC that once you select the top end CPU are just under $5000 and the iMac Pro starts at $5000.

It would be very strange for Apple to produce a product between the 2. But the other major issue for apple if they did the i9 would be that they would need to start at 10core otherwise they would not have enough PCIe lanes to have 4 thunderbolt ports and a GPU. The lower core i9 chips just don't have enough PCIe so you're still talking about a $1k CPU that would put the price of the i9 iMac around the same as the 8core iMac Pro.

Yes some users need single core performance but more users need multi core performance in the long run if intel can't complete on not just price but also IO (PCIe and memory bandwidth is much larger with AMDs solution compared to Xeons) apple may be forced (if they care about the pro pro user) to look into using a mix of intel and AMD across thier platforms.

If you are going to comment about CPUs, at least get the details correct.
i9 runs at 140 watt to 165 watt, it is not capable of ecc ram either.
ECC ram is single bit error correcting code, capable of recovering from a single failure.

As the performance of iMac Pro is required to be better than simply settling for AMD's latest inadequacies, they use intel Xeon.

 

[CWallace]

As the performance of iMac Pro is required to be better than simply settling for AMD's latest inadequacies, they use intel Xeon.

They're using Xeon because of ECC support and the Xeon line is designed to provide stable and consistent performance over time.

The i9's are enthusiast chips for folks playing games or competing in benchmarking competitions and I imagine Intel expects them to often be overclocked with exotic cooling systems keeping them within thermal limits.

 

[hishnash]

If you are going to comment about CPUs, at least get the details correct.
i9 runs at 140 watt to 165 watt, it is not capable of ecc ram either.
ECC ram is single bit error correcting code, capable of recovering from a single failure.

As the performance of iMac Pro is required to be better than simply settling for AMD's latest inadequacies, they use intel Xeon.

> i9 runs at 140 watt to 165 watt, it is not capable of ecc ram either.

that is the listed TDP but if you look at reviews using this part in the wild they are seeing much higher power draw even when the CPU is not boosting. There is some discussion that this might be due to bad bios optimizations but we don't know for sure yet.

I dont think I said the i9 supported ECC? the above comment from me was me explaining why I think apple did not produce a iMAC with i9 between the i7 and the Xeon.

> AMD's latest inadequacies

not sure you have been following on the AMD chipset line, what inadequacies are you referring to? The only thing i can think of would be the single/2core boost speeds are little lower than the intel parts.

There is also a slightly higher maximum inter module latency. But given that macOS kernel is under the control of apple would be very well able to optimize the scheduler to avoid inter die module communication as much as possible by placing tasks memory etc on the local CCX. Communication within the CCX on Zen is faster than on the SkylakeSP in the end it is a traid off with no clear winner.

The IPC of Zen is a bit lower than SkylakeSP true but the floating point performance is significantly higher.

The memory bandwidth is higher than SkylakeSP.

It would be possible to clock the Zen cores up to 4gz (even a 16core part will boost all cores to this)

overall for the iMac Pro that is not extensible, there may not be a clear winner between the 2. But for the Mac Pro (supposedly modular) coming 2018? i could see an Epyc based system being significantly better. Remember as of the new year you will no longer need to get intel validation to use thunderbolt3 so they will not be able to stop apple putting thunderbolt3 on such a system. I dont see apple doing a 2P macPro so the eypic with 32cores, and 2TBs of ECC memory will most likely be enough.
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They're using Xeon because of ECC support and the Xeon line is designed to provide stable and consistent performance over time.

The i9's are enthusiast chips for folks playing games or competing in benchmarking competitions and I imagine Intel expects them to often be overclocked with exotic cooling systems keeping them within thermal limits.

And for the macPro do you think they will stick with intels Xeons or make the jump over to amds new Epyc platform?

 

[CWallace]

And for the macPro do you think they will stick with intels Xeons or make the jump over to amds new Epyc platform?

I expect it to be Purly Xeons on LGA 3066 in probably single and dual socket configurations.

 

[pankajdoharey]

No, ARM on desktops will remove the ability to run non-app store apps and games, along with no windows bootcamp.
It will also be slower than the retina macbook.
It is not realistic at all to sabotage the high performing desktops for a silly dream.

I don't think That is a problem, Apple has done it in the past, with Rosetta Stone Binary Translation Technology when they moved from PowerPC architecture to Intel. I don't see why it can't be done once again.

 

[kiwipeso1]

I don't think That is a problem, Apple has done it in the past, with Rosetta Stone Binary Translation Technology when they moved from PowerPC architecture to Intel. I don't see why it can't be done once again.

No, Apple does not get to rewrite the laws of physics. It can not be done, and it is not a matter of blind faith as you would suggest.
The fact that you do not understand the underlying idea does not mean that you are correct when you talk about it.

It is simple logic, and not a matter of metaphysical nonsense to will a result in your favour.

 

[pankajdoharey]

No, Apple does not get to rewrite the laws of physics. It can not be done, and it is not a matter of blind faith as you would suggest.
The fact that you do not understand the underlying idea does not mean that you are correct when you talk about it.

It is simple logic, and not a matter of metaphysical nonsense to will a result in your favour.

Can you please state what simple logic you are referring to? I stated my reason why it can be done, since it has already been done in the past.

 

[kiwipeso1]

Can you please state what simple logic you are referring to? I stated my reason why it can be done, since it has already been done in the past.

It is simple logic, as in electronics logic gates. The circuitry does not support processing a more sophisticated logic set than is present in ARM hardware, as that would require either a dedicated intel processor negating the benefits of the ARM CPU, or process the data several times slower than the same clock speed intel CPU, due to differences in the reduced instruction set chip compared to complex instruction set chip.

The previous transition was from RISC to CISC, and therefore a speed boost was achieved to allow for emulation in real time during the snow leopard era.
However, CISC to RISC will result in a backwards step even below the performance of the retina macbook toy.

As the rules of physics dictate the operation of electronics, it is not possible to use ARM in place of intel at anywhere near the same performance of macs just out of supported lifecycle.
Therefore, it is not rational to suggest that Apple should turn the mac into a glorified iPad.

 

[pankajdoharey]

It is simple logic, as in electronics logic gates. The circuitry does not support processing a more sophisticated logic set than is present in ARM hardware,.

.
First of all it is clear you dont know anything about either electronics or Processors. A RISC architecture for the same die size in silicon can be made faster than a CISC processor simply because a RISC requires a lot less number of transistors per unit area. Which leaves room for expansion on the Die to more processing cores, registers, and memory controller. CISC on the other hand has too many complex instructions, these instructions are required to be decoded through a microcode interface. Which eventually end up requiring a lot of space on the silicon just for instruction set decoding logic. And leaves less space for actual computing machinery. Also Many RICS Processors can execute multiple instructions per clock cycle CISC cannot. I suggest you read the differences between these architectures and how they work before arguing falsely.

 

[kiwipeso1]

First of all, my father invented and patented a new type of processor in 1972, it is still in use as a assembly line manufactory process regulator to this day, and has helped that company maintain a perfect production record for cigarette manufacture for over 40 years.
He is considered the discoverer of that entire class of circuit, and it is capable of managing basic functions such as elevator automation.
I learnt electronics in 1982, and my contributions include currently working on the 16th generation of my new type of processor since Jan 2014, which is aimed at a hardware implementation of a new type of decision making assistant program of my design with interaction with my new type of database program.

Furthermore, as my experience with electronics and computing design goes back to primary school, along with advanced mathematics to the stage where I have 24 new topics and algorithms in maths and computer science; it is fair to say that I know this basic science better than most lecturers in the topics do.
And so, it comes to merely your opinion debating a qualified scientist in his fields of study of the last 35 years.
I do not have the time to educate you on where you can learn how to do the most elementary study, I would suggest you try IIT university.

 

[Mago]

Also Many RICS Processors can execute multiple instructions per clock cycle CISC cannot.

All modern CPU are RISC, even Modern Intel i7/Xeons, they still use CISC (or WISC) instructions set, but they decodes these instructions into RISC instructions before sent it to the execution pipelines (an execution pipeline proceses a instruction sequence in FIFO mode as the instructions completes a new instruction behind its pre-processed, allowing faster IPC rates -instructions per clock cicle, now higer IPC record its hold by.

Multiple Instructions per Cycle execution, is what commercially Intel names Hyperthreading, and in HPC its named SMT simultaneous multi-threading https://en.wikipedia.org/wiki/Simultaneous_multithreading, faster IPC record holder is for Intel i9-7900X at about 12.75, closest AMD its Ryzen 1700x at 10.23, both based on 7Zip benchmark, it may vary wide about benchmark focused on transcoding or fp64 etc, it its just a case.

Bench based on IPC are moreles useles, as some cpu trades IPC for much higher frequency or memory bandwidth delivering better total IPS and perf per watt, which actually its much more important.

I don't know Ryzen Threadripper IPC performance figures yet, but should be very close to 1700X.

 

[pankajdoharey]

First of all, my father invented and patented a new type of processor in 1972, it is still in use as a assembly line manufactory process regulator to this day, and has helped that ,......

Yeah Sure and i got the Nobel price in 1972.
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All modern CPU are RISC, even Modern Intel i7/Xeons, they still use CISC (or WISC) instructions set, but they decodes these instructions into RISC instructions before sent it to the execution pipelines (an execution pipeline proceses a instruction sequence in FIFO mode as the instructions completes a new instruction behind its pre-processed, allowing faster IPC rates -instructions per clock cicle, now higer IPC record its hold by.

Multiple Instructions per Cycle execution, is what commercially Intel names Hyperthreading, and in HPC its named SMT simultaneous multi-threading https://en.wikipedia.org/wiki/Simultaneous_multithreading, faster IPC record holder is for Intel i9-7900X at about 12.75, closest AMD its Ryzen 1700x at 10.23, both based on 7Zip benchmark, it may vary wide about benchmark focused on transcoding or fp64 etc, it its just a case.

Bench based on IPC are moreles useles, as some cpu trades IPC for much higher frequency or memory bandwidth delivering better total IPS and perf per watt, which actually its much more important.

I don't know Ryzen Threadripper IPC performance figures yet, but should be very close to 1700X.

My initial point was that the moment you add a instruction decoding logic to the processor to decode a complex instruction into a many simpler (RISC) instructions. You've wasted a huge portion of the die only on decoding logic which which does not add anything to compute cores. The compute cores would still need to fetch simple instructions to be executed. I agree to your point that modern CPU's have absorbed many RISC features, but none of these CISC processors have been able to perform beyond 2 threads per core (Hyperthreading). On the other hand it was very common of RISC architectures like MIPS, to have 3,4,5,6 threads per core. This is attributed to the delay in processing complex ISA, Which makes RISC a faster and better architecture.

 

[Mago]

you add a instruction decoding logic to the processor to decode a complex instruction into a many simpler (RISC) instructions. You've wasted a huge portion of the die only on decoding logic which which does not add anything to compute cores.

That's only makes the CPU more expensive not slower, but you save a huge amount of data traffic switching from RISC to CISC instructions set you save a lot of cpu time loading instructions from RAM by instead decoding it on tthe Die, even Intel's announced x86 succesor architecture will ditch any native x86 instruction and implement a new WISC instruction set and a special legacy decoder just to keep backward compatibility optimizing both processing and data traffic while breaking with few inherited x86 bottlenecks.

but none of these CISC processors have been able to perform beyond 2 threads per core (Hyperthreading). On the other hand it was very common of RISC architectures like MIPS, to have 3,4,5,6 threads per core.

Thats not true, Hyperthreading (SMT) maxed only to 4 SMT in production silicone only on Xeon-Phi and IBM's BlueGene (not mainstrem CPU), MIPS stay at 2-Way SMT. https://en.wikipedia.org/wiki/Simultaneous_multithreading

HT/SMT neither are the magic pill, HT/SMT means some process that implement mutiple threads (with the same code) on different data can process 2 thread at same time concurrently, few algorithms benefit from it, mostly things like video encoders, data compresson, cyphers, few Niche Process benefit from somthing beyond 2-Way SMT.

Adding HT also has an side effect: power hungry cpu, note Intel's Xeon-D multi core server cpus are single threaded, tose Xeon-D are as efficient as some ARM based Server cpu. check https://stackoverflow.com/questions/23078766/is-hyperthreading-smt-a-flawed-concept .

Note ARM tested SMT but have never release it since it raises power consumption.

 

[pankajdoharey]

That's only makes the CPU more expensive not slower, but you save a huge amount of data traffic switching from RISC to CISC instructions set you save a lot of cpu time loading instructions from RAM by instead decoding it on tthe Die, even Intel's announced x86 succesor architecture will ditch any native x86 instruction and implement a new WISC instruction set and a special legacy decoder just to keep backward compatibility optimizing both processing and data traffic while breaking with few inherited x86 bottlenecks.




Thats not true, Hyperthreading (SMT) maxed only to 4 SMT in production silicone only on Xeon-Phi and IBM's BlueGene (not mainstrem CPU), MIPS stay at 2-Way SMT. https://en.wikipedia.org/wiki/Simultaneous_multithreading

HT/SMT neither are the magic pill, HT/SMT means some process that implement mutiple threads (with the same code) on different data can process 2 thread at same time concurrently, few algorithms benefit from it, mostly things like video encoders, data compresson, cyphers, few Niche Process benefit from somthing beyond 2-Way SMT.

Adding HT also has an side effect: power hungry cpu, note Intel's Xeon-D multi core server cpus are single threaded, tose Xeon-D are as efficient as some ARM based Server cpu. check https://stackoverflow.com/questions/23078766/is-hyperthreading-smt-a-flawed-concept .

Note ARM tested SMT but have never release it since it raises power consumption.

I think you have a point, this debate in useless the differences between CISC and RISC have diminished. Thankyou.

 

[pankajdoharey]

This might be interesting Microsoft is bringing x86 Emulation to AMR64 this fall to Windows 10 http://www.zdnet.com/article/micros...-windows-10-redstone-3-fall-2017-deliverable/

 

[Mago]

This might be interesting Microsoft is bringing x86 Emulation to AMR64 this fall to Windows 10 http://www.zdnet.com/article/micros...-windows-10-redstone-3-fall-2017-deliverable/

I name it Retro-Optimization.