Excuse my dumbness but arnt all transistors 3d? Even on a tiny proccessor they're not totally flat are they.
Guess im missing something but what is it?
The standard name of the "3D transistors" is FinFETs.
You're right that the transistors are 3D, but the gate isn't; its a single plane, these new transistors will have 3D planes.
You're right that the transistors are 3D, but the gate isn't; its a single plane, these new transistors will have 3D planes.
They even invented 3D planes? It is a new era for geometry as well!![]()
Would that be a Sandy Bridge or an Ivy Bridge?![]()
That cracked me up... Thanks for the laugh.
It's not about dislike what we have now. The current design is beautiful. It's about wanting more. like a greedy child lol. I'm just curious as to what apple comes up with next
I wonder the difference between this and the Arms chips now.
Can they actually surpass the Arm in capacity and battery life?
No, there are power consumption differences inherent in the ISAs that Intel cannot overcome with process improvements alone.
... and those are?
for one Intel chips have a lot more cache on the CPU to keep the most used instructions on the CPU die. most of the processor die these days is cache
even with the A6, ARM CPU's will only be at the xbox 360/PS3 level of power while the new consoles that will come out soon will be even faster.
for one Intel chips have a lot more cache on the CPU to keep the most used instructions on the CPU die. most of the processor die these days is cache
... and those are?
This difference in decoding logic between a CISC and RISC architecture is the first that comes to mind.[/url]
But in the end - both will run similar numbers of operations to do the task. x64 reads fewer instructions, and expands them into primitive operations. RISC reads (and decodes) more primitive instructions.
There are some extremely power-hungry RISC chips out there (Alpha, POWER, ...).
There are other small differences such as how register dependent an architecture is.
If there's a measurable difference in the power consumption from a memory operation vs. a register operation, OK - but at the implementation level register renaming reduces the effect.
But in the end - both will run similar numbers of operations to do the task. x64 reads fewer instructions, and expands them into primitive operations. RISC reads (and decodes) more primitive instructions.
There are some extremely power-hungry RISC chips out there (Alpha, POWER, ...).
If there's a measurable difference in the power consumption from a memory operation vs. a register operation, OK - but at the implementation level register renaming reduces the effect.
Apples A6 is going to use this same 3D Tri-Gate Technology. Should be interesting.![]()