Most likely using 4 x 8GB memory chips. Likely have to give up some latency advantage as there're definitely delays incurred when trying to move memory from chip to CPU's memory controller via mux circuitry. I don't think it is using a wide memory bus.Hmm, not sure. Maybe they are using four 8GB chips instead of two like the M1. Or maybe someone besides Samsung makes them? Good catch.
For the M1, it looks like it is using a 128-bit data channel supplied by both 4/8GB LPDDR4X memory chip. Each access of memory will send 128-bit data from/to memory to/from M1 with minimal access latency.