Do you believe that? What's more likely, that Apple uses N3 to make a slower CPU or that they use a horizontally scaler A16/M2 on the already relatively mature N5P? Not to mention that these scores are 100% in line with M2 performance (just add a P-cluster).
You are making up stuff I didn't write. It isn't slower. All the benchmarks here are faster than M1. So 'slower' isn't really an issue. What you are trying to present is "slower than it could have been". Well the M1 Ultra could have had more PCI-e outputs if Apple had put them. Woulda-coulda-shoulda isn't a factor of 'slower'.
The same architecture (IPC) attached to the same generational memory (and bandwidth) and run at about the same clocks is probably going to turn in the same scores. However, if it is smaller then they it cheaper to make (more dies per wafer). And if optimized for better power utilization, then better perf/watt.
N3 doesn't mandate that the clocks have to go faster or that the chip dies have to be "as big as possible" (i.e., throw an even bigger kitchen sink of stuff onto the integrate 'everything' die) .
Swimming with the next generation GPUs
www.tomshardware.com
TSMC N3 is a bit of a dual edged sword. They are trying a bit to compensation for memory dropping off the density gain track by having FinFlex ( 3 different FinFet options available on a single die). That is a work-around , but the trade-off is that the wafer costs are even higher.
Apple isn't shipping "race to the bottom pricing' SoC , but their SoCs are not immune to price elasticity issues either. ( e.g, when inflation drives Mac prices higher... people complain. ). Apple SoCs have a high price but if production costs increase that will eat into the margins.
Just mastering N3 new complexities (where to use the 'flex' and where not and how to juggle the tradeoffs across the whole SoC die is going to be a hard enough problem without throwing "brand new micro architecture implementation issues at it at the same time. ) . I don't think it is likely Apple wants to throw maximum complexity at a first iteration N3 implementation. Same issues that AMD is running into are going to hit Apple also at smaller fab implementation nodes.
Apple's SoC implementations have tended throw higher than normal level of cache at trying to push the performance curve harder with lower overall power consumption. If memory detaches from the same density trend curve that the compute logic is coupled to .. that gets harder to do while keeping the die costs about the same. (implementation area doesn't shrink, but the wafer area costs more).
The Pro sized die is under less pressure than the Max sized die , but if Apple is keeping those two coupled at the fab process implementation. A smaller Pro size die isn't going to 'hurt' getting high volume out of fewer wafers either.
Back when Intel was closely following the tick/tock improvements were steady and chips came out roughly "on time". Intel threw everything and the kitchen sink at Xeon Max ( sapphire rapids) and it is late. From an engineering project risk management perspective those two outcomes are really not all that surprising.
Apple has timely implementation issues to manage also.
To me it's disappointing because I want three things. First, a split between consumer and prosumer desktop hardware.
You are mixing up two things here. Consumer (laptop) and prosumer desktop. The consumer desktop Mac is going to be a high performance laptop SoC. Really was that way on Intel (x86) so not sure why there would be an expectation that it would change for the M-series. The Mini and new iMac 24" enclosures are not big boxes with very high airflow throughput. For a long time the Mini was relatively crippled because the CPU cores took up such a high share of the overall TDP budget that you couldn't put any substantive GPU in there. So the consumer desktop Mac and consumer laptop Mac are likely going to remain coupled.
The higher end desktop hardware CPU cores are likely not going to get decoupled from laptop/mobile origins. That is the volume that pays the R&D bills. Basically the same thing for the GPU cores.
The Mac Studio backs off the "thinnest" enclosure constraints, but not by a huge amount.
There probably be a splt on implementation when the larger laptop CPU and GPU cores drive a bigger disconnect with demands for a larger L3/System Level cache that is going to stop scaling as well. Probably going to bring a different disaggregation implementation ( e.g., AMD moving memory controllers and cache off central die) than completely different core design/implementation.
Second, new generation of P-cores (so far we had three generations of Apple Silicon on what is essentially the same P-core frontend and backend, with just few incremental tweaks and new instructions).
If jumping up and down to stay on the older N5 family implementation why would that change? If try to go to a much larger P-core complex implementation then production costs go up (consume more die area ). But wouldn't be able to move the GPU performance forward with more cores there. E cores got more focused improvements which have lower die area consumption impact.
And when P-core improvements come there is pretty good chance it would be more weighted toward AMX/SIMD impact that into hot rod single thread drag racing. (more compute on tightly structured and/or clustered data than on even bigger caches and even deeper speculative execution. )
Third, competition with x86 in the desktop segment. These M2 Max scores are enough to secure a lead among laptops in first half of 2023, but Apple is getting outgunned in the desktop space.
70+ % of what Apple sells is laptops. So winning where they sell the most. Consumer desktops. Not really outgunned there either ( average Windows desktop isn't shipping with a mid-upper range dGPU in it ). So even smaller gap area. Those are pretty much where the "M2 Pro" and plain M2 would be going.
in the upper end of desktop space , Apple is more so being 'outgunned' by software than hardware. macOS is capped at 64 threads. Where AMD/Intel are 100+ threads to high end desktops. There are zero 3rd party GPU drivers on macOS on M-series. macOS on Intel dropped Nvidia, but Apple has dropped everyone else . That is a bigger 'hole' than hardware. More than one CPU or GPU package to the gunfight will lead to being outgunned. Apple bring one SoC (gun) and the other options bring 2-4 xGPU packages to the fight.
