M4+ Chip Generation - Speculation Megathread [MERGED]

[tenthousandthings]

Do you think… I know it’s too early to comment on this and it’s pure speculation, but do you think the M6 generation will be a small upgrade focused on just adopting the 2nm tech, with minor improvements to performance and efficiency? Maybe they will focus on the Neural Engine this time? Or will they use the jump to this new tech (including the new GAAFET transistors) to introduce deep architectural changes.

Integral to the N2 (2nm) transition is a change to the packaging across the board, from InFO to WMCM. I think the takeaway is that the M6 and M7 generations will see a wave of hardware redesigns, incorporating these changes in arrangement, thermals and thickness. So OLED isn't the only reason a MacBook Pro redesign is coming with M6. I think the iMac is also a prime candidate for an M6 redesign. My guess is the others will wait for M7, with the MacBook Air leading the way with an early release like the M2.

Here is a "slide" (despite the look of it, it is not a TSMC slide) based on comments made by TSMC to local Taiwan media (Commercial Times and others) during a tour in late January:

 

[Antony Newman]

I think Apple (and ARM) are keen this greatly reduce the perf/watt of running (smaller) LLMs on device.

ARM will probably try an incorporate more of this into the v10 ISA (in the next few years).
There is speculation that Apple will incorporate (more) LLM/AI optimisations in their Neural Engine (NPU).

We don’t know what the memory bandwidth the M5 Ultra Apple will offer; It will be interesting to see if Apple have to ramp this up in the M6 to avoid on chip congestion limiting performance scaling.

 

[tenthousandthings]

Here is a prediction I made in one of the news threads:

• Apple A19, A19 Pro, M5, M5 Pro/Max/Ultra = TSMC N3P (2025-2026)
• Apple A20, A20 Pro, M6 = TSMC N2
• Apple M6 Pro/Max = TSMC N2 (no M6 Ultra)
• Apple A21, A21 Pro, M7 = TSMC N2P
• Apple M7 Pro/Max/Ultra = TSMC A16 (2028)
• Apple A22, A22 Pro, M8 = TSMC A14
• Apple M8 Pro/Max = TSMC A14 (no M8 Ultra)
• Apple A23, A23 Pro, M9, M9 Pro/Max/Ultra = TSMC A14P (2029-2030)

This covers TSMC's transitions both [1] from FinFET to Nanosheet (gate-all-around) transistors and [2] their hop-step(s) to Super Power Rail (backside power delivery network) architecture.

I'm lumping the A-series and the root M-series together, and then separating that from the Pro/Max/Ultra M-series. This distinction, however, isn't neatly reflected in Apple's "platform names" for the silicon after the A15-M2 generation, which do not align with the process nodes, and instead are staggered, with the M-series one step behind the A-series:

• A12 Bionic = H11P; A12X = H11G
• A13 Bionic = H12P
• A14 Bionic = H13P; M1 = H13G; M1 Pro/Max/Ultra = H13S/C/D
• A15 Bionic = H14P; M2 = H14G; M2 Pro/Max/Ultra = H14S/C/D
• A16 Bionic = H15P; M3 = H15G; M3 Pro/Max300/Max400/Ultra = H15S/M/C/D
• A17 Pro = H16P; M4 = H16G; M4 Pro/Max = H16S/C
• A18 = H17A; A18 Pro = H17P; M5 = H17G; M5 Pro/Ultra = H17C/D
• A19 = H18A; A19 Pro = H18P; M6 = H18G

I don't know much anything about these "platform names" -- these are from Ilikeiphone123 -- but they make sense (the A18 Pro MacBook launching alongside the M5 MacBook Air, for example, assuming that happens), and I think this list lines up with other rumored mentions of them in Apple's OS builds.

I'd be curious if anyone has any insight into what they are, and if this is accurate.

 

[novagamer]

Okay, we’ve seen that just as predicted on this thread, the M5 received a focus on the GPU, on its performance and the AI processing capabilities of the GPU.

Do you think… I know it’s too early to comment on this and it’s pure speculation, but do you think the M6 generation will be a small upgrade focused on just adopting the 2nm tech, with minor improvements to performance and efficiency? Maybe they will focus on the Neural Engine this time? Or will they use the jump to this new tech (including the new GAAFET transistors) to introduce deep architectural changes.

I personally think the Neural Engine will remain quite untouched, aside from the gains of a higher clock speed. But I see Apple more interested in enhancing the CPU and GPU neural accelerators for some reason. Also, the same way they implemented a completely new architecture for the M5 CPU e-cores, I think they will do the same with the M6 CPU p-cores, completing the revamp of the CPU architecture.

I’m not sure if the M6 update will be similar to the M3, which was a bit “in between” and short lived, or if the M5 will be that type of chip and the M6 will be a more solid foundation for the next generation Apple Silicon.

If the timing is correct it seems to me that M6 may be the interim cycle / proving ground for 2nm, and M5 will last a while at the high end in Studios with an Ultra variant.

I remember hearing years ago that M7 was in planning and there were significant changes coming but who knows how accurate it was. I think it was the same source who said Jade 4C was being canceled (which turned out to be true) and the concept would be revisited around that time ~2027/2028.

 

[Populus]

If the timing is correct it seems to me that M6 may be the interim cycle / proving ground for 2nm, and M5 will last a while at the high end in Studios with an Ultra variant.

I remember hearing years ago that M7 was in planning and there were significant changes coming but who knows how accurate it was. I think it was the same source who said Jade 4C was being canceled (which turned out to be true) and the concept would be revisited around that time ~2027/2028.

Nah, there are also other factors that push me to the M5 gen and not to wait for the M6, such as the rising prices of RAM and SSDs.

Today I’ve read a rumor that Kioxia has doubled the price of NAND storage and Apple has had to accept. No idea if it will be reflected in the upcoming M5 Macs, but if it isn’t, it will be worth buying now because I’d say it’s almost granted the SSD and RAM upgrades will be even more expensive in the future…

Let’s cross our fingers for the M5 gen to retain the same upgrade prices…

 

[name99]

People know that one of my minor obsessions has been alternative ways to get use out of the ray tracing unit.
I think I've found my first genuine candidate!

Take a look at (2026) https://www.ssslab.cn/assets/papers/2026-lian-UniSTC.pdf Uni-STC: Unified Sparse Tensor Core.
This is a really nice idea. The problem to be solved is providing an accelerator for sparse linear algebra (eg dense matrix times sparse vector, sparse matrix times sparse matrix, etc). The big ideas are
1. whatever compression scheme is used to compress the sparse arrays, that is pre-processed before the accelerator to generate a (temporary) bitmap indicating zero vs non-zero elements. This bitmap may be directly loaded from memory (it's one reasonable way to indicate a sparse vector/matrix) or it may be constructed on demand by some auxiliary HW in parallel with loading in the sparse vector/matrices.
2. we have essentially three async HW loops each connected by queues.
The outermost loop considers items at a 16*16*16 granularity using an outer product bitmap to figure out which of the 16*16 calculated spots might be non-zero.
Any time the resultant 16*16 tile is non-zero it's passed on to the next stage which considers the 16*16 tile at a 4*4*4 granularity, figuring out which particular 4-element dot products will be non-zero.
Descriptors for these non-zero 4-element dot products are passed to the final stage which then performs the dot product.
The details are in the paper. This is all rather nice! And, except for extremely sparse matrices, works better than other known solutions.

However what caught my eye was that there are many similarities between what's being done here and what's being done in the ray tracing unit. Both basically walk a data structure performing simple auxiliary calculations and waiting on memory so that they can occasionally feed some genuine computational work to the primary GPU datapath.
It feels like it shouldn't be too difficult to augment the existing ray tracing unit with these ideas, and thereby have a mechanism that can substantially boost the performance of sparse linear algebra (which is, of course, probably going to be helpful to AI).
And once the idea has been validated in the GPU something similar could probably be added to ANE.
And even maybe to AMX? (The fit to AMX is not so great, though it is feasible, especially maybe if you shard your large computation over multiple cores so that each of these sparse pre-processors is working simultaneously. I want to see it attached to AMX for the selfish reason that science other than just AI wants to use sparse linear algebra, and AMX is the only place where we have FP64.)

 

[thejadedmonkey]

Do you think… I know it’s too early to comment on this and it’s pure speculation, but do you think the M6 generation will be a small upgrade focused on just adopting the 2nm tech, with minor improvements to performance and efficiency?

The m6 is rumored to be a physical form factor change, so Apple will likely go light on tech changes, relying on the form factor and touchscreen to sell the device. Except the m7 refresh to bring the performance.

 

[Populus]

The m6 is rumored to be a physical form factor change, so Apple will likely go light on tech changes, relying on the form factor and touchscreen to sell the device. Except the m7 refresh to bring the performance.

Yeah… I think N3P is a mature process and a solid upgrade with the M5… although we don’t have a crystal ball, but other factors such as the RAMmageddon and the NANDpocalypse are highly pushing me to stop waiting and get the Mac mini ASAP. Let’s hope it gets released on March 4th along with the MacBooks, otherwise maybe I’ll have to grab the M4.

 

[innerproduct]

So what are your thoughts on the new m5 max chips? It seems to align well with conjecture here and setting the stage for very interesting "Ultra "class chips.

 

[crazy dave]

So what are your thoughts on the new m5 max chips? It seems to align well with conjecture here and setting the stage for very interesting "Ultra "class chips.

The switch to a new "performance" core (with the old "performance" core becoming the "super" core) is interesting - very similar to the approach Intel and Qualcomm take of having middle cores (and some other ARM designs are doing this as well).

 

[Pressure]

The most interesting thing about M5 Pro and Max is that they apparently are multiple dies on a single substrate instead of a single monolithic die.

The chips are built using a new Apple-designed Fusion Architecture. This innovative design combines two dies into a single system on a chip (SoC)

 

[Luftkopf]

The most interesting thing about M5 Pro and Max is that they apparently are multiple dies on a single substrate instead of a single monolithic die.

I wonder if this approach will improve yields? Seems like it should at first glance.

 

[Pressure]

I wonder if this approach will improve yields? Seems like it should at first glance.

Definitely. Also the monolithic die of the Max was getting quite big.

This means that they can still use the CPU die with defects (to the TB5 controller, cache, CPU cores, media engine etc.) as the M5 Pro this generation.

 

[deconstruct60]

The switch to a new "performance" core (with the old "performance" core becoming the "super" core) is interesting - very similar to the approach Intel and Qualcomm take of having middle cores (and some other ARM designs are doing this as well).

Which Qualcomm cores are these? The Oryon cores for Snapdragon 8 Elite is just two levels.

"...Rather than a mix of large, medium, and small CPU cores as it has used in the past, the 8 Elite has two “Prime” cores for hitting that high peak clock speed, while the other six are all “Performance” cores that peak at a lower 3.53 GHz. ..."

Qualcomm brings laptop-class CPU cores to phones with Snapdragon 8 Elite

New CPU cores replace more complicated mix-and-match of CPU architectures.

arstechnica.com

if talking about the non-Nuvia evolution stuff that is still on Arm design IP ... that isn't a good match to what Apple is doing here.

Intel also is a couple generations away from 'unifed core' implementations.

This appears more like AMD's cloud cores where they stripped the max single thread drag racing elements out of the design and shrink the footprint of the 'large' core into something laid out smaller. Save space so can have more cores but don't 'give away' much on the what is implemented. The Apple E-cores are in a very different zone of giving up space and more enhanced lower energy savings.

Apple is never using all three in same die. Super+E or Super+P but no Super+P+E. In any one system implementation there is no 'middle'. [ Having 3 different one makes the OS scheduling more painful, for probably little impact. ]

 

[deconstruct60]

Definitely. Also the monolithic die of the Max was getting quite big.

Doesn't 'help' the "dual Max' configuration either. Super duper chunky things pretending to be chiplets are not very good chiplets.

This means that they can still use the CPU die with defects (to the TB5 controller, cache, CPU cores, media engine etc.) as the M5 Pro this generation.

the Pro and Max didn't mismatch when it came to TB5 controller. Media engine could easily bein on the GPU die...

The defect issue with the CPU chiplet is probaly mostly because it is much smaller (if eject all of the GPU and Memory controller stuff). Fewer overall defects means don't 'have to' use it on the Max configurations (because substantively fewer of them).

This appears to be somewhat going back to the M1 era where getting some savings but just doing one CPU subsection, but physically splitting the die ( instead of mostly growing extra GPU onto a Pro die design. )
Suggestive that the Max has a bigger GPU chiplet so the binning variances there are more so only the larger chiplet.
( or stringing multiple binned GPU chiplets there if the GPU/Memory is subsectioned there. ) Just switching focus on which chiplet is binned to just one package.

 

[DrWojtek]

Doesn't 'help' the "dual Max' configuration either. Super duper chunky things pretending to be chiplets are not very good chiplets.





the Pro and Max didn't mismatch when it came to TB5 controller. Media engine could easily bein on the GPU die...

The defect issue with the CPU chiplet is probaly mostly because it is much smaller (if eject all of the GPU and Memory controller stuff). Fewer overall defects means don't 'have to' use it on the Max configurations (because substantively fewer of them).

This appears to be somewhat going back to the M1 era where getting some savings but just doing one CPU subsection, but physically splitting the die ( instead of mostly growing extra GPU onto a Pro die design. )
Suggestive that the Max has a bigger GPU chiplet so the binning variances there are more so only the larger chiplet.
( or stringing multiple binned GPU chiplets there if the GPU/Memory is subsectioned there. ) Just switching focus on which chiplet is binned to just one package.

I noticed the GPU comes in 16 or 20 and 32/40 cores. Suggesting one GPU die is up to 20 cores and the Max chiplet using two of these. Either two binned ones or two perfect ones.

 

[deconstruct60]

I noticed the GPU comes in 16 or 20 and 32/40 cores. Suggesting one GPU die is up to 20 cores and the Max chiplet using two of these. Either two binned ones or two perfect ones.

But Apple said.

" ... The chips are built using a new Apple-designed Fusion Architecture. This innovative design combines two dies into a single system on a chip (SoC), which includes ...
...
All-New Fusion Architecture
M5 Pro and M5 Max introduce the Apple-designed Fusion Architecture, a state-of-the-art design that connects two dies into a single SoC. ... "
https://www.apple.com/newsroom/2026...supercharge-the-most-demanding-pro-workflows/

They are talking bout both the Pro and Max there. ( Seems more like Fusion 2.0 than "all new" Fusion because combining two dies is what they have done with the Ultra for a couple of iterations. The interconnect tech is likely better and the size of the individual dies is getting closer to actual chiplet oriented design, but generally the same approach done at higher overall unit volume. The dies mated not being exactly the same size is a big leap for "all new" label. )

Just as easily with the same breakdown be two GPU chiplet dies. One almost as large as old Max and one much smaller that are each in turn paried with just one CPU chiplet variant.

The larger die could be just binned down more because it is more likely to run into more defects than the smaller GPU die. (even binned down to 32 it is still 12 higher than the smaller 20 count GPU chiplet). The amounts are just the sub-group GPU core clusters that can be cleaning switched off as a group. That wouldn't change on a larger die.

Two use two GPU dies with one CPU chiplet likely would mean that the GPU chiplets would then get two Fusion connectors. That is more space to 'connecting' that it is to computing. Also more complicated packaging (one bridge expanding into two bridges on a larger base die. )

 

[leman]

The logical choice would be to have a CPU+IO die (same for Pro and Max) and a GPU die (different for Pro and Max). This would be the best use of economies of scale and optimal die manufacturing sizes. This strategy furthermore aligns with earlier leaks and with the chip info from the Chinese sources that was posted here before.

 

[DrWojtek]

The logical choice would be to have a CPU+IO die (same for Pro and Max) and a GPU die (different for Pro and Max). This would be the best use of economies of scale and optimal die manufacturing sizes. This strategy furthermore aligns with earlier leaks and with the chip info from the Chinese sources that was posted here before.

This article draws the same conclusion:

M5 Pro and M5 Max are surprisingly big departures from older Apple Silicon

Apple is using more chiplets and three types of CPU cores to make the M5 family.

arstechnica.com

 

[leman]

This article draws the same conclusion:

M5 Pro and M5 Max are surprisingly big departures from older Apple Silicon

Apple is using more chiplets and three types of CPU cores to make the M5 family.

arstechnica.com

Yep, all of this makes total sense to me except this bit

everything in the GPU die seems to be doubled, implying that Apple is, in fact, sticking two M5 Pro GPUs together to make one M5 Max GPU

I don't think they are stacking two GPU tiles, they are likely using a "chopped" floorpan just like they did with Pro and Max dies before. Here, the 2x chip is manufactured as a single die, but the IP blocks are repeated, and the floorpan is designed in such a way that the mask can be "cut in half" and still yield a functioning chip.

 

[diamond.g]

I do find it interesting the base M5 Max has a different bandwidth config than the full part, even though the Pro doesn't have the same "limitation". Do we know if the memory controllers are on the GPU, IO, or CPU die?

 

[Basic75]

Do we know if the memory controllers are on the GPU, IO, or CPU die?

Do we already know there are three different dies and these are it?

 

[leman]

I do find it interesting the base M5 Max has a different bandwidth config than the full part, even though the Pro doesn't have the same "limitation". Do we know if the memory controllers are on the GPU, IO, or CPU die?

Until now, memory controllers have been closely tied to the SLC cache as each controller "owns" a slice of the cache. This means that the controllers are likely to be on the same die as the SLC cache. If the cache is split between two dies, I'd expect to see memory controllers on both. If the cache is only present on the GPU die (which is a likely possibility), then the memory controllers will be there.

 

[diamond.g]

Do we already know there are three different dies and these are it?

That is a pretty big assumption on my part.

 

[diamond.g]

Until now, memory controllers have been closely tied to the SLC cache as each controller "owns" a slice of the cache. This means that the controllers are likely to be on the same die as the SLC cache. If the cache is split between two dies, I'd expect to see memory controllers on both. If the cache is only present on the GPU die (which is a likely possibility), then the memory controllers will be there.

It seems like the cache would follow the GPU, but it also makes the Pro-> Max GPU tiling more sus because the bandwidth of the Pro smaller pro should have half the smaller Max, but isn't. But then again the smaller Pro has less CPU cores, so maybe the memory controller follows it?