M4+ Chip Generation - Speculation Megathread [MERGED]

[deconstruct60]

Perhaps I’m misremembering, but isn’t there a mainstream rumor that there will be no M6 Pro/Max? If so, then there may never be an M6 Mini.

the mainstream rumors is that the ‘plain’ MBP 14” will ship with M6 and the revised upper division will ship with M5 Pro/Max with different non SoC centric features. Suggestive that the M6 isn’t faster on substantive multithreaded jobs. The Studuio currently ships with M4 Max and M3 Utlra. The same mismatch could exist for Mini M6 and Mini Pro M5 Pro if there is no M6 Pro/Max. That isn’t a show stopper.

If the max RAM capacity of a M5 Pro is much larger than the plain M6 , then the maintain of buying minis to run small- midsize local LLM will keep Mini Pro sales as high as they are now.


The mini is likely delayed not because there is no M6 Pro, but that there is no ‘extra’ memory for M6 or M5 Pro . Memory is already hobbling M4 mini availability. That probably doesn’t improve if switch to memory that M5 and M6 need.

The rumors are that the MBP M6 and iMac M6 . That is likely enough to suck up the flow. After the initial demand bubble fades there a bit Apple can roll out the Mini ( and depending on how deep the fade also MacStudio ) . If somehow Rhoda’s products flopped then the mini and Studio would ship incrementally sooner. ( in part why the iMac is coupled to MBP 14” . It can suck up small levlels of underflow if MBP moves significantly under projections. If both over projections then FOMO fears boost the number of folks who commit to officially waiting in queue. )

Holding the Mini to the M4 past Q1 2027 would be a giant competitive misstep. Gettin the plain MBP 14” off the M5 should free up M5 class memory consumption that can shift to installing the Mini. ( worst case if M6 memory was too overly restricted then they could move mini to M5 / M5 Pro … it would ship and still would have clarity on where upgrading from M4 made sense or not )

I think the biggest area for improvement with A20/M6 is the introduction of hybrid WMCM packaging.

Probably not. Chiplets in and of themselves didn’t make the M5 Pro/Dramatically faster.

for the A20 Pro WMCM taking the RAM from on top of the logic chip might. ( better thermal at cost of larger 2D footprint. ) . But if memory is still stacked on top then only a smaller incremental gain. The wires between the memory and chip got shorter and narrower.,but still memory chip primarily is a physical block of the chip from heat sink.

But the A-series Pro is already relatively small (90-100 mm^2) . The plain A series is incrementally smaller than that . The plain M series is not all that big either ( 150-170mm^2) . AMD Zen 5 cpu chiplet is in 70-80mm^2 range .

We know TSMC is “all-in” with it,

They might be “all in” but also only have limited capacity . Both the entire A and plain M volume at the same time ? Probably not.

but I don’t think it’s clear exactly how it will change iPhone/iPad silicon. I would expect Apple to focus on improved thermals.

The M-Series already do not stack memory on top. haven’t since most of the AnX series.

 

[tenthousandthings]

They might be “all in” but also only have limited capacity . Both the entire A and plain M volume at the same time ? Probably not.

As I understand it, WMCM replaces InFO-POP for N2 and beyond. It’s not optional. It’s a hybrid approach that incorporates InFO concepts, however, so it remains to be seen what has really changed.

 

[deconstruct60]

As I understand it, WMCM replaces InFO-POP for N2 and beyond. It’s not optional.

More likely more economical for the increasingly narrow cases that justify N2 than technically required.

There is a push to do more die to die thinnest, shorter wire traces rather the older, thicker Redistribution Layer(RDL). of older InFO approaches.

InFo-POP and InFO-oS are complements here.

https://3dfabric.tsmc.com/english/dedicatedFoundry/technology/InFO.htm

InFO-PoP

versus InFO-So.

If just flip the right 'Logic' to RAM then basically the same approach just much , much finer lines/circuits between the two logic tiles.

If this is accurate depiction of WMCM

TSMC's WMCM Revolutionizes Chiplet Design with Heterogeneous Integration | Steven Wu posted on the topic | LinkedIn

We spend a lot of time obsessing over the race to 2nm and beyond. But if you’re watching the HPC and AI hardware space closely, you know the real bottleneck isn't just transistor density anymore, it’s interconnects. This is where TSMC’s Wafer-Level Multi-Chip Module (WMCM) technology is quietly...

www.linkedin.com

Then is mostly evolutionary from InFO-So -> InFo-LSI -> WMCM. The major issue those that it is for most part side-by-side. If could get 300-400 chips from a wafer for the A-series die ( lie the first path above) then not going to put al to put all of those on the second path if there are also RAM stacks also soaking up 2D footprint on that 'packaging wafer'. The power efficiency, bandwidth efficiency, and intergration when waaaaaay, up but the 2D footprint got bigger to do that. If only get 200-300 diced package out of it the Wafers/Month of the process is a limiter.

A couple of articles have suggested that

"...
3. TSMC’s WMCM capacity may reach 60,000 wafers per month by end-2026 and exceed 120,000 wafers per month in 2027.
..."

https://medium.com/@kumari.sushma661/tsmc-expands-wmcm-packaging-for-apples-2nm-chips-capacity-to-double-by-2027-fca4e1ca8c51

60,000 is a large amount , but if need 10M A20 Pro dies a month there isn't a big gap there. ( If need another 10M A20 a month then even less so. )

If the Memory-die-stack to wafer interface is fixed by TSMC then perhaps it is 'required' for this packaging process (using a standard design library). But if had a N2 chip and used another packager you would be absolutely required to do something exactly like these because of some property of N2? I would be skeptical.

Note also that the M5 (and previous ) all took two memory stacks. Two stacks on a wafer is going to squeeze out even more room from the even larger M6 die. How many packages per wafer going to get then?

It’s a hybrid approach that incorporates InFO concepts, however, so it remains to be seen what has really changed.

If get rid of package-on-package verticle properties it is a big change in trade-offs.

 

[name99]

Diamond is a lot more thermally conductive than copper due to heat being transferred by phonons. Graphene is also more thermally conductive than copper when the transfer is parallel with the plane.

As a followup to this, I just saw an ad (from a reputable Japanese company, not some fly by night nonsense) for a new type of cold plate that's essentially a copper slab, then a silver diamond slab, then copper fins. The silver diamond is a matrix of silver and artificial diamond granules. (The diamond transports the heat, the silver binds the granules together.)
This same tech is also being touted for eg cooling high power lasers [high power in this context means a few 100mW, which may not seem much but is confined to a tiny volume].
As a comparison,
- a pure copper cold plate has a thermal conductivity of 400W/mK (obviously for that particular area)
- the composite is 600
- pure silver diamond is 1000
A diamond film should be even better...

 

[IvyKing]

- a pure copper cold plate has a thermal conductivity of 400W/mK (obviously for that particular area)
- the composite is 600
- pure silver diamond is 1000
A diamond film should be even better...

Thermal conductivity of natural diamond is ~2,200W/mK, diamond with substantial depletion of 13C supposedly comes in at 3,200W/mK. The higher thermal conductivity of nearly pure 12C diamond is due to lesser amounts of phonon scattering from the 13C atoms.

 

[deconstruct60]

What will be the real difference between the M4 and M6 chips? I am thinking about possibly upgrading to the M6 Mac Mini when that comes out.

Two less Super Cores than M5. but gain back the 4 Performance ("midrange " ) cores had in the M4. So total aggregate is up 2 CPU cores.

It is a better tweak toward running multiple, concurrent multithreaded loads. But definitely endowed to win the single threaded drag race as opposed to being a M4 Pro 'killer'.

The major uplift to a core type subsystem is to NPUs. Dual 16 cores ( e.g., Apple can run one of their frameworks while perhaps someone else runs something else tuned a bit differently. Or two different Apple ones at the same time. 🙂 )

Apple's marketing numbers versus M4 on their webpage ( have to click for more info on M6 and M5 Pro and relative to the M1 )
LLM Prompt Processing. 13x. ( M4 2.8x )
Excel. 2.3x. ( M4 1.6x )
Photo Editing 3.2x. ( M4 1.8x )
Music. 2.7x. ( M4 1.4x )
3D Rendering 10.3x ( M4 4.8x )
Gaming (relative to M4 ). 2x

The M5 Pro vs M4 Pro. ( baseline M1 Pro)

LLM Prompt Processing 22x ( M4 Pro 5.6x )
Excel. 4.6x. ( M4 Pro 2.7x )
Photo Editing 5.5x ( M4 Pro 3.7x )
Music 4.6x ( M4 Pro 4.4x )
3D Rendering 15.9x ( M4 Pro 11.3x )
Gaming ( relative to M4 Pro ) 1.5x

P.S. Excel is a mixture of single and multithreaded work. There is no huge jump with the M6 to overwhelm just having many more cores.

 

[deconstruct60]

Sadly Apple is still being a bit vague here with M5 Ultra introduction. Still no package pictures of M5 Max or M5 Ultra.
As opposed to M5 Pro/Max intro they did add some more detail about the Fusion connection.

".. M5 Ultra uses UltraFusion to connect two dual-die M5 Max chips to form the quad-die architecture — a first for Apple silicon. UltraFusion increases the inter-die bandwidth to over 4.4TB/s and the connection density by over 6x. ..."

Apple introduces M6 and M5 Ultra for a big leap in performance and AI compute

Apple debuted M6 in the new Mac mini and M5 Ultra in the new Mac Studio, providing an extraordinary leap in performance and AI capabilities.

www.apple.com

But seems like the same "New fusion" architecture from M5 Max. the M3 Ultra connector bandwidth was 2.2TB/s

"...

• Apple’s custom-built UltraFusion packaging technology uses an embedded silicon interposer that connects two M3 Max dies across more than 10,000 signals, providing over 2.5TB/s of low-latency interprocessor bandwidth, and making M3 Ultra appear as a single chip to software.

..."

Apple reveals M3 Ultra, taking Apple silicon to a new extreme

Apple today announced M3 Ultra, offering the most powerful CPU and GPU in a Mac.

www.apple.com

Connection density up 6x and bandwidth up not 6x means not necessarily a magical panacea when TSMC says t hey have new trick to crank up the density.


The memory bandwidth is up

" ... Additionally, M5 Ultra features a massive amount of high-bandwidth unified memory, up to 512GB, and delivers a staggering 1.2TB/s of unified memory bandwidth that is 50 percent higher than M3 Ultra. ..."

but 1.200GB/s is basically 2x the Max.

" .. Max supports up to 128GB of unified memory with higher unified memory bandwidth up to 614GB/s. ..."

Apple debuts M5 Pro and M5 Max to supercharge the most demanding pro workflows

Apple today announced M5 Pro and M5 Max, the world’s most advanced chips for pro laptops, powering the new MacBook Pro.

www.apple.com

It is a quad die package ... just not the one folks were talking about for last 4-5 years. Now need 4 dies to get a equivalent of two Max-like SoCs into the package.