I didn't find it in a quick search, but it could be out there (ran GPGPU search, and on Tesla 2075, not by a particular application/suite).
But it should follow SLI/Crossfire scaling, so there is relevant information out there (biggest problem is lane count available to designers; past 36 lanes on LGA1366, they need an nF200 chip).
Example article.
And what this information shows, is though there is a performance loss, it's not that much (less than 5% between 8x and 16x lane slots for the same card and benchmark according to the article from Tom's Hardware).
I expect that 4x of those lanes will be reserved for QPI communications, as is the case with LGA1366/X58, but hasn't been clearly stated so far.
As per PCIe 3.0, that may come after the LGA2011 parts release, due to the lack of suitable components/devices to test with (PCISIG testing specs aren't even finalized <last I checked a week or so ago anyways...>).
The real advantage IMO however, is that it's possible to double the lane count in a DP system (80 lanes total). Assuming there is a reserve for QPI, then 72 lanes will remain for slots (could actually get 6 * 16x slots + 2* 4x lane slots for a GPGPU
beast from Hades workhorse).
😱 😀