OK cool, name a RISC architecture.
And before you offer ARM: FJCVTZS has made the idea that ARM is still RISC completely absurd.
How about I name some RISC architectures for which I've designed actual microprocessors?
MIPS, F-RISC, PowerPC, ARM, Sparc
FJCVTZS is a RISC instruction. It reads from registers, performs a pipeline computation, and puts the result in a register. It does not require multiple trips through the pipeline, it does not read operands from or write results to memory, it does not need to be broken into micro-ops that are individually scheduled and retired. It does not have an arbitrary or variable instruction length. Its operands are found in the same location as other instructions. The instruction decoder need not be stateful to understand the instruction.
"RISC" doesn't mean "simple instructions" or "few instructions."