Re: Re: but you don't
Originally posted by Tooth
The memory controller is a perfect point. Each CPU on an AMD MP system has FOUR TIMES the memory bandwidth that the G4 has.
Four times the effective BUS bandwidth, not four times the memory bandwidth
AMD SMP Architecture - lame ascii art :
CPU <-> 2.1GB - \
**************| - memory controller - <-> 2.1GB - memory
CPU <-> 2.1GB - /
Each cpu hence gets about half the memory bandwidth to work with (but it can use the additional FSB bandwidth to do other things like talk directly to PCI/AGP devices etc)
G4 SMP Architecture - lame ascii art :
CPU - \
***** | <-> 1.3GB - Memory Controller <-> 2.7GB/s - memory
CPU - /
Each CPU gets around 1/4th the memory bandwidth, but between them they get half of the bus bandwidth each.
(so the G4 has _HALF_ the Athlons per processor bandwidth in an SMP config, not one quarter) (this of course excludes situations where more memory bandwidth to a single processor would be hugely beneficial.)
OTOH, the Athlon doesn't have any L3 cache, and that is BOUND to help a huge amount if the dataset fits into the L3 cache. (hmm, are the caches on the PPC 7455 inclusive or exclusive?)
the ideal (IMO) would be point to point links from the processors to the memory controller and a memory subsystem that could keep them both fed, like so :
CPU <-> 2.1GB/s \
**************|- Memory controller - 4.2GB/s - Memory
CPU <-> 2.1GB/s /
