Re: Re: Re: For all you whiney lamers out there:
Originally posted by mischief
Find me the words "Front Side Bus" ANYWHERE in the description of the new mobo and I'll relent. Finding it on a PC website doesn't cout, it must be from Apple's resources.
The fact that Apple doesn't call it the "front side" bus doesn't mean that it isn't one.
The frontside bus is the link from the processor to the system controller (and hence memory controller) the backside bus is the link from the processor to the L2 or L3 cache (well, both, I'm unsure if there are seperate backside buses on the G4 for the L2 and L3 caches.)
Actually I am perfectly aware of how DDR and QDR works, my point is that you seem to be under the impression that there have been NO changes to chip architecture to support DDR
If the bus interface on the G4's in the new PowerMacs is DDR, why are apple only claiming 1.3GB/s throughput for it?, are you suggesting they are using a 32bit DDR bus @ 167Mhz ?
you are in fact GUESSING that the newest G4 has no DDR support. Again, back it up from the horses mouth and I'll leave you alone.
167Mhz SDR / 64Bits wide = 1.3GB/s
Apple are claiming the Bus between the G4's and the system controller on the new Powermacs is?... 1.3GB/s
Apple Specs page
"Up to 167MHz system bus supporting over 1.3GBps data"
Also note that all the parts that ARE DDR are labelled as such (the L3 cache and the memory)
Look at any Intel CPU beginning with the P2 or most AMD CPU's recently. Have you ever wondered why the card is roughly the size of a VHS cassette and has 2 fans?
I suggest you look at an Intel or AMD cpu released after the middle of '00
Where's the second chip?, that's the only processor the machine I'm sitting at contains...
Failing that, here's an intel processor from 1998 with the heatsink removed
There's only the one chip on that... (the backside is bare *ahem*)
There are 2 chips, and I can tell you right now that beginning with the P2 the common practice has been to just add the numbers up and call it a speed.
Total nonsense, the P2 slot 1 was a processor core and two external Sram chips (L2 cache) same for the slot A Athlon
If you can find me a photograph of a slot 1/A processor with multiple CORES on it that hasn't been photoshopped, I will be EXTREMELY impressed.
All this would actually mean something if a PPC used a mobo in exactly the same way as an x86 chip.
The bus logic is different, big deal.. you can't put a Pentium 4 on an Athlon board either, or a Pentium 3 on a Pentium 4 board, not only are the sockets physically different, but electrically too.
I'm pretty sure you couldn't just stick a PPC daughter card on a PC mobo and magically get it to work.
Obviously not, there is the endian issue, and the total electrical layout incompatability issue, doesn't mean it's impossible to rework the chipset to interface to a PPC bus however, especially if the chipset were a modular design anyway (Nvidia's Nforce exists in both GTL+ and EV6 versions for example)
There is an inherent cost in the custom mobo neccesary to tie PPC to the data paths correctly.
Your point?, there's an inherent cost to designing any new piece of circuitry.
(note, at what point have I suggested putting G4's on current x86 boards?... hint: never.)
Not to mention the Unique socket issue of the ZIF tech.
changing the physical layout of the socket is trivial compared to the work needed to reengineer the bus logic of the chipset.
Argueing that there are cheap alternatives without engaging the reality of HW R&D
The reality of R&D seems to be that Motorola can't be bothered to do any, they clearly know how to do DDR signalling, they just don't seem to think that the 74xx line is important enough to bother adding it to the main bus, even though it would DRASTICALLY improve altivec performance on large datasets.
a PowerMac is NOT cheap, and it is rather irking to pay a large sum of money for old tech, the new Powermacs even up a lot of that, but the processor <-> system controller bus (call it what you will) is still circa 1999 technology.. even if it is clocked a tad higher (gee whizz, 33Mhz extra!)
Originally posted by mischief
Find me the words "Front Side Bus" ANYWHERE in the description of the new mobo and I'll relent. Finding it on a PC website doesn't cout, it must be from Apple's resources.
The fact that Apple doesn't call it the "front side" bus doesn't mean that it isn't one.
The frontside bus is the link from the processor to the system controller (and hence memory controller) the backside bus is the link from the processor to the L2 or L3 cache (well, both, I'm unsure if there are seperate backside buses on the G4 for the L2 and L3 caches.)
Actually I am perfectly aware of how DDR and QDR works, my point is that you seem to be under the impression that there have been NO changes to chip architecture to support DDR
If the bus interface on the G4's in the new PowerMacs is DDR, why are apple only claiming 1.3GB/s throughput for it?, are you suggesting they are using a 32bit DDR bus @ 167Mhz ?
you are in fact GUESSING that the newest G4 has no DDR support. Again, back it up from the horses mouth and I'll leave you alone.
167Mhz SDR / 64Bits wide = 1.3GB/s
Apple are claiming the Bus between the G4's and the system controller on the new Powermacs is?... 1.3GB/s
Apple Specs page
"Up to 167MHz system bus supporting over 1.3GBps data"
Also note that all the parts that ARE DDR are labelled as such (the L3 cache and the memory)
Look at any Intel CPU beginning with the P2 or most AMD CPU's recently. Have you ever wondered why the card is roughly the size of a VHS cassette and has 2 fans?
I suggest you look at an Intel or AMD cpu released after the middle of '00
Where's the second chip?, that's the only processor the machine I'm sitting at contains...
Failing that, here's an intel processor from 1998 with the heatsink removed
There's only the one chip on that... (the backside is bare *ahem*)
There are 2 chips, and I can tell you right now that beginning with the P2 the common practice has been to just add the numbers up and call it a speed.
Total nonsense, the P2 slot 1 was a processor core and two external Sram chips (L2 cache) same for the slot A Athlon
If you can find me a photograph of a slot 1/A processor with multiple CORES on it that hasn't been photoshopped, I will be EXTREMELY impressed.
All this would actually mean something if a PPC used a mobo in exactly the same way as an x86 chip.
The bus logic is different, big deal.. you can't put a Pentium 4 on an Athlon board either, or a Pentium 3 on a Pentium 4 board, not only are the sockets physically different, but electrically too.
I'm pretty sure you couldn't just stick a PPC daughter card on a PC mobo and magically get it to work.
Obviously not, there is the endian issue, and the total electrical layout incompatability issue, doesn't mean it's impossible to rework the chipset to interface to a PPC bus however, especially if the chipset were a modular design anyway (Nvidia's Nforce exists in both GTL+ and EV6 versions for example)
There is an inherent cost in the custom mobo neccesary to tie PPC to the data paths correctly.
Your point?, there's an inherent cost to designing any new piece of circuitry.
(note, at what point have I suggested putting G4's on current x86 boards?... hint: never.)
Not to mention the Unique socket issue of the ZIF tech.
changing the physical layout of the socket is trivial compared to the work needed to reengineer the bus logic of the chipset.
Argueing that there are cheap alternatives without engaging the reality of HW R&D
The reality of R&D seems to be that Motorola can't be bothered to do any, they clearly know how to do DDR signalling, they just don't seem to think that the 74xx line is important enough to bother adding it to the main bus, even though it would DRASTICALLY improve altivec performance on large datasets.
a PowerMac is NOT cheap, and it is rather irking to pay a large sum of money for old tech, the new Powermacs even up a lot of that, but the processor <-> system controller bus (call it what you will) is still circa 1999 technology.. even if it is clocked a tad higher (gee whizz, 33Mhz extra!)
