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nForce Speculation
- Thread starter arn
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Re: etoils
FYI, Nvidia's nForce 415 series is "Nforce1" without the onboard graphics...
(iow, both nforce 1 and 2 are complete chipsets)
And even the boards that DID have onboard video also had an AGP slot (might be exceptions that I'm unaware of though?)
Asus Nforce mainboard
FYI, Nvidia's nForce 415 series is "Nforce1" without the onboard graphics...
(iow, both nforce 1 and 2 are complete chipsets)
And even the boards that DID have onboard video also had an AGP slot (might be exceptions that I'm unaware of though?)
Asus Nforce mainboard
I too think there's a chance the new Power Macs could use a modified variant of the nForce2 SPP/MCP-T chipset with a couple additons.
4 dimm slots
10/100/1000 ethernet (No DualNet)
various other Mac specific changes.
Right now the biggest bottleneck is the bus between the processor and the memory. nForce with the Athlon provides two channels of DDR memory. I believe the idea is that the processor (with the nForce) can only use about half of the available bandwidth wile the left over bandwidth can be used by the "IGP" or integrated graphics processor. The lowly consumer nForce actually provides some features that put it above the similar vintage VIA and AMD chipsets. Also, the nForce motherboards sill provide a complete AGP slot that will bypass the integrated video. Some friends of mine have done this.
While I think is very possible that Apple may be working with AMD on a nForce type chipset for the Mac, I do not think that the pictures we have seen have any relevance to this issue. The positioning and angle of the chips is a function of the PCB CAD program. You might tell the CAD program what chips are where, what leads connect to what, and how many layers of PCB it has to route through. Placing the chip at a 45 degree angle could be either to shorten or neaten the routing of the paths or perhaps just to show off the fancy new chip on the board.
Well, the bottleneck from the cpu to ram is significant, the bottleneck of ATA/133 is bigger. Master/slave combinations kill performance. Yeah sure we can have 2 drives on each ata bus, but the cpu is in use to determine which drive to use for what each and every time the drive is accessed. I'm surprised that serial-ata isn't on this chipset. It's the future, no more bus architecture for hard drives, all serial baby.
45 angle means nothing
If the speculation that Apple will use nforce technology is based on the fact that the nForce has a tilted northbridge, then it's full of bunk. MSI boards use that sort of arrangement all the time, and most of their northbridges come from VIA. And, VIA is the largest controller chip company in the industry. The fact that nForce tilts theirs is to reduce trace length, and therefore signal interference between components. Nothing revolutionary, or nonstandard here, the industry has been doing it for years. I'm not saying apple won't use an nVidia mobo in the future (god only knows what they're up to anyhoo), but this is certainly no indication that they will.
If the speculation that Apple will use nforce technology is based on the fact that the nForce has a tilted northbridge, then it's full of bunk. MSI boards use that sort of arrangement all the time, and most of their northbridges come from VIA. And, VIA is the largest controller chip company in the industry. The fact that nForce tilts theirs is to reduce trace length, and therefore signal interference between components. Nothing revolutionary, or nonstandard here, the industry has been doing it for years. I'm not saying apple won't use an nVidia mobo in the future (god only knows what they're up to anyhoo), but this is certainly no indication that they will.
From the nForce2 pdf:here
"NForce2 processors offload processing tasks from the cpu to deliver unmatched system performance.
and an optimized 128-bit architecture reducing overall system latency.
With its efficient memory design and support for 3GB of 400 MHz DDR memory, nForce2 eliminate system bottlenecks and speed up everyday media-rich applications"
Of course, all these specs are referring to nForce2 being used with AMD cpus,
but I'm guessing they've developed one for the mac platform too.
"NForce2 processors offload processing tasks from the cpu to deliver unmatched system performance.
and an optimized 128-bit architecture reducing overall system latency.
With its efficient memory design and support for 3GB of 400 MHz DDR memory, nForce2 eliminate system bottlenecks and speed up everyday media-rich applications"
Of course, all these specs are referring to nForce2 being used with AMD cpus,
but I'm guessing they've developed one for the mac platform too.
Chryx:
Of course I said that exact same thing about how AMD can run dual Athlons with dual FSB's in my post. I have built several such machines.
Scottgfx:
There are actually two busses between the processor and memory, the FSB and the RAM's bus (which is not called "Rambus" cause that's a freaking company name). CPU's with only a single bus between memory and themselves are those with on-die memory controllers, such as AMD's Hammer series and I think Moto's 85xx series.
But however there is NO performance edge offered by current dual-channel nForce1's over single-channel DDR chipsets, such as the VIA KT333. Without a FSB fast enough to use it all, there is really no point to dual-channel DDR except if you happen to be using the built-in graphics (which the entry-level G4 towers could reasonably do, although I'd rather see somethng faster).
rugby:
Eh, only if you are grinding on disk all day. I'd take more memory system bandwitth any day (still running 5400RPM disks!).
topicolo:
Yeah, it sucks just like all the other integrated video setups except nForce.
OVERALL, I'd have to say that this rumor is silly, the 45deg angle of the chipset is meaningless, the nForce2 is not generaly useful to Apple, the nForce2 needs changes to both FSB and network controllers to work for Apple, and that no DDR FSB G4 is known to exist at this time. THere is no reason to suspect that this chipset will be used by Apple, and I would be surprised if it were.
Of course I said that exact same thing about how AMD can run dual Athlons with dual FSB's in my post.
I have built several such machines.Scottgfx:
There are actually two busses between the processor and memory, the FSB and the RAM's bus (which is not called "Rambus" cause that's a freaking company name). CPU's with only a single bus between memory and themselves are those with on-die memory controllers, such as AMD's Hammer series and I think Moto's 85xx series.
But however there is NO performance edge offered by current dual-channel nForce1's over single-channel DDR chipsets, such as the VIA KT333. Without a FSB fast enough to use it all, there is really no point to dual-channel DDR except if you happen to be using the built-in graphics (which the entry-level G4 towers could reasonably do, although I'd rather see somethng faster).
rugby:
Eh, only if you are grinding on disk all day. I'd take more memory system bandwitth any day (still running 5400RPM disks!).
topicolo:
Yeah, it sucks just like all the other integrated video setups except nForce.
OVERALL, I'd have to say that this rumor is silly, the 45deg angle of the chipset is meaningless, the nForce2 is not generaly useful to Apple, the nForce2 needs changes to both FSB and network controllers to work for Apple, and that no DDR FSB G4 is known to exist at this time. THere is no reason to suspect that this chipset will be used by Apple, and I would be surprised if it were.
Re: Re: Confusion
No, it doesn't mean AGP 4X runs at AGP 6X speeds.
AGP nX refers to the the real speed of the bus in relation to 66MHz bus. 1X=66MHz, 2X= 133MHz, 4X=266MHz.
The AGP spec states that the AGP bus is 32bit wide. There is NO double wide AGP bus (remember a standard SDRAM/DDR bus is 64bits wide, an interlaced bus is 128 bits wide)
This has NOTHING to do with system memory. AGP 4X provides [266MHz x 32bit] 1066 MB/s maximum through put.
AGP is its OWN bus. It doesn't matter if the main memory bus uses a ga-jillion way dimm setup and it has a petabyte/sec of throughput... AGP 4x is still AGP 4x.
Please, don't make stuff up.
No, it doesn't mean AGP 4X runs at AGP 6X speeds.
AGP nX refers to the the real speed of the bus in relation to 66MHz bus. 1X=66MHz, 2X= 133MHz, 4X=266MHz.
The AGP spec states that the AGP bus is 32bit wide. There is NO double wide AGP bus (remember a standard SDRAM/DDR bus is 64bits wide, an interlaced bus is 128 bits wide)
This has NOTHING to do with system memory. AGP 4X provides [266MHz x 32bit] 1066 MB/s maximum through put.
AGP is its OWN bus. It doesn't matter if the main memory bus uses a ga-jillion way dimm setup and it has a petabyte/sec of throughput... AGP 4x is still AGP 4x.
Please, don't make stuff up.
haha, not in a million billion years.
You have no idea what nVidia would need to do in order to re-engineer an x86 chipset with an athlon bus in order to make it work with a Mac. Here is the short list....
It's the wrong endian
It is designed to issue x86 instructions! (how do you throw an x86 interrupt to a PPC processor?)
It is designed to interface with the wrong processor bus.
It doesn't know what the hell Open Firmware is.
It isn't designed to bootstrap from Mac ROM.
It would be (no joke) about as easy to make a nForce2 mac as it would be to make a PPC Athlon. Realistically, some of these issues are easer to tackle than others, but together they are a show stopper.
IF (and this is a HUGE if), nVidia makes a PPC compatable chipset, it would only be architecturally similar to nForce... it would have to be considered a different, new chipset.
NO, ATA/133 is NOT a bottleneck. The ONLY exception to this is master/slave which isn't really a bottleneck issue, but rather a design problem.
ATA/133 has 133MBYTES/sec of throughput. The fastest 7200rpm IDE drives don't sustain transfers much over 35MB/sec.
Current ATA standards are NOT a bottleneck... they have significantly more bandwidth than any one or two drives can even burst out.
The real issue with IDE is the poor design of the master/slave model... but this is easily overcome by adding channels.
Re: Re: Re: Confusion
You're forgetting, the ONBOARD gf2MX on the Nforce is plugged straight into the "system controller" rather than being on the other side of the AGP bridge....
According to Nvidia it's theoretically equivalent to AGP @ 6x
'tis something of a moot point if there isn't memory bandwidth free for it however.
You're forgetting, the ONBOARD gf2MX on the Nforce is plugged straight into the "system controller" rather than being on the other side of the AGP bridge....
According to Nvidia it's theoretically equivalent to AGP @ 6x
'tis something of a moot point if there isn't memory bandwidth free for it however.
Just a heads up, we already know that the NForce is fairly modular in this regard, as it's been seen with both GTL+ (Xboxs use a variant of the Nforce chipset with meatier graphics hardware and a Pentium 3) and EV6 buses (Athlon/desktop Nforce)
Oh
The fastest 7200rpm IDE drives don't sustain transfers much over 35MB/sec.
Heads up number 2, Western Digital WD1200JB's can push about 50MB/s sustained.
Re: nForce Speculation
Geez, please stop posting this crap as likely rumor. This is totally wishful thinking...
Chip position doesn't mean anything. Not one hairy thing. That statement automatically qualifies the original rumor monger as a moron.
Second problem with the rumor...
nForce DOESN'T USE A NORTHBRIDGE!!!!!
The nForce chipset (and nForce2) doesn't use a traditional northbridge/southbridge design (neither do the newer intel p4 chipsets). Anyone who knew anything about the nForce would have known this.
The rumor is total, unmitigated, crap.
Please kill this line of rumors already. Apple already has a DDR chipset in production. I'll eat my hat if they don't use the same chipset in the next Mac towers.
Geez, please stop posting this crap as likely rumor. This is totally wishful thinking...
Chip position doesn't mean anything. Not one hairy thing. That statement automatically qualifies the original rumor monger as a moron.
Second problem with the rumor...
nForce DOESN'T USE A NORTHBRIDGE!!!!!
The nForce chipset (and nForce2) doesn't use a traditional northbridge/southbridge design (neither do the newer intel p4 chipsets). Anyone who knew anything about the nForce would have known this.
The rumor is total, unmitigated, crap.
Please kill this line of rumors already. Apple already has a DDR chipset in production. I'll eat my hat if they don't use the same chipset in the next Mac towers.
If we want to pick nits:
pcextreme reviewed the drive you mentioned.
First off, this is a special edition drive and it is currently (to the best of my knowledge) the fastest IDE drive available... aside from the $20k solid state devices.
Second, here are the benchmarks...
sequential read, 47MB/sec
random read, 8MB/sec
The fastest transfer possible is 82MB/s which is a burst from the whopping 8MB of on drive cache.
Even 2 of these drives couldn't use up ATA/133 bandwidth on a sustained read... even if all the data was on one contiguous block. That would never happen though, because the IDE won't let you access a master and slave at the same time.
Even the best IDE drive available can only burst about 2/3s of ATA/133s bandwidth. I think my assertion still stands. This drive can sustain less than 1/2 of ATA/133s bandwidth with a totally contiguous block of data (no seeking).
RAID is excellent for writing, but horrid for reading. So you would be able to Write large file very fast, and safely, however reading them back would take longer. I thing the Screen Savers posted some benchmarking scores, and found that on average, RAID is slower than standard Master/Slave. The only reason to use RAID, is for the security of redundancy.
Also on IDE RAID, you still can't write, or read from more than one disk at a time. That is part of IDE.
There are different kinds of RAID, the two found most often are:
RAID 0 : Striping
literally slices the data into chunks and simultaniously writes/reads from all disks (provides a pretty much 100% boost to read/write speeds compared to a lone drive)
RAID 1 : Mirroring
maintains a live hardware backup, some controllers interleave the reads (gives a RAID0 like read performance increase)
(there's also things like RAID 0+1, which is a stripeset with a live mirror)
I would imagine the tests you saw were for RAID-5?