Re: Re: Re: Re: Power5 at Hot Chips
Originally posted by MisterMe
The original PowerPC was the POWER chip set reduced to a single chip. The Power 4 and soon to be Power 5 are single chip implementations of a more advance POWER architecture. In a sense, the already thin lines between PPC and POWER have blurred. The ISA's are the same except for a couple of instructions added to the PPC 601 (for transition purposes) and AltiVec. Apple used POWER-based IBM RS/6000 workstations to port System 7 to the PPC.
In reality the original POWER chip was a chip set (5 or 7 chips made up the original CPU). It was considered a
very big deal when IBM got it down to a single chip. This single chip version still had the POWER label, NOT the PowerPC label. After getting it to a single chip IBM created other single chip variants including the RAD6000 (a radiation hardened, space qualified version). All of these were called POWER chips. POWER was originally an acronym:
Performace
Optimized
With
Enhanced
RISC. The "opmised with enhanced RISC" was based upon optimizations and enhancements from the original IBM RT CPUs.
The PowerPC was originally envisioned as a very different chip. It was concieved by Apple, IBM and Motorola (the original AIM group). It was to be a combination of the best parts of the single chip version of the IBM POWER CPU and the best parts of Motorola's 88000 chip set (which had one through 5 chips in the CPU chip set depending upon the exact confinguration used). This combination was to be tuned to the Macintosh System (as it was called back then -- System 6 reigned at that time. Pink was a functional lab experiment. Rhapsody and OS X were not even on the horizon.)
Since the instructions sets were very similar all the compiler houses used the IBM RS/6000 workstations to experiment with their codes and compilers. This included not only Apple, but also MetroWorks (who early on had a MUCH better compiler than Apple), Green Hills, Absoft, and others. The PowerPC 601 was very similar in instruction set to the single chip version of the POWER CPU. The 601 (the long forgotten 602), the 603, 604 and "G3" did not have the AltiVec/Velocity Engine instructions.
Additionally, the various chips have had different levels of symmetric multiprocessing. The first one to have the full standard MERSI set was the 604. The 603 had only MEI (thus BeOS had to do most of their cache checking and such in software). If I recall correctly the G4 has MESI but not the full MERSI. I have not checked on what the G5 has.
Originally posted by akac
Well, for one thing - deriving a 9xx processor from a Power5 is going to be a lot of work. We'll probably see it at some point, but probably not for another couple years at best. You don't just run a processor design through a "make for desktop use" macro or something. It took IBM and Apple several YEARS to get the 970 from the Power4 which has been around for awhile.
Of course the Power5 is being built with the 9xx in mind, so it should be easier, but still not anything they'll introduce next summer.
Yes, it does take a couple years or more to design a chip -- even a derivative chip. However, the original POWER4 was not designed to have a direct derivative PowerPC. There are many, many rumors floating around suggesting the POWER5 was designed with making a PowerPC derivative in the plans from the beginning. Additionally, it has been heavily rumored that there exists an IBM team which has been working on a PowerPC derivative of the POWER5 for almost a year now. Even though these are just "rumors", I doubt it will be two years from now before there exists a PowerPC derivative of the POWER5.
Originally posted by Mudbug
So at this point it safe to call this thing vaporware....
No, the POWER5 is definitely not vaporware. There currently exist systems in test based upon the POWER5. These are server class systems. People don't buy the bleading edge of these systems. They want to know IBM has tested them for several months in various configurations before they ship systems to the enterprise. There are exceptions of course (including the DOE and other USGov organizaitons), but most large enterprises will only commit to these high end server systems after a company had tested them thoroughly in-house first. Large enterprises won't commit the resoures to install these until they can be assured the uptime is not like the typical desktop.
Originally posted by Mudbug
As for the 970/980 130nm/90nm question - will there be a really significant speed gain by moving to the 90nm process for the 970, or is that mostly for power consumption/heat? If it's speed, then I wonder if the smaller-process 970 might be a speed equivalent of the larger-process of the 980, but what do I know?
nothing... that's why I guess a lot.
[/B]
In reality we all know nothing. The sum total of what we know divided by what we don't know would definitely cause an underflow error on any currently shipping computer system (or in the case of the old Burroughs systems -- which used BCD for computations and the only limit on precision was the amount of memory you had -- a memory overflow resulting in a null answer anyway.) Thus by current binary computations we all know nothing.
Will a die shrink from 130nm feature size to 90nm feature size give a significant performance improvement? Is 15 to 30 percent improvement significant to you? For most people, probably not. For some people who have highly compute bound processes, maybe so.
No one knows what the performance improvement will be in the POWER5 derivative versus the PowerPC 970. Even the people within the system clearly state any hard number predicted for improvement is pure conjecture. There will be improvement. Of that you can be assured, but exactly how much is pure conjecture -- and probably will be for at least 9 or more months from now.
My apologies for this being sooooo long winded.
