PowerMac G5 2.5GHz Benchmarks

[ddtlm]

dguisinger:

HOWEVER: Most multi-bus systems actually combine all the buses with PCI-PCI bridges, therefore grouping some bottlenecks, but ultimately access to the main CPU/memory still remains a bottle neck of the main PCI bus. Apple doesn't state how they designed their chipset.

Perhaps that was true once, but its not anymore. Apple's G5 PCI-X chip appears to be an AMD chip (AMD-8131) which sprouts no less that 3 PCI/PCI-X busses which are totally independent and connected, through the chip, to HT and from there into the system RAM through the northbridge (which is on-CPU for an AMD chip). The Sun machines I've speced recently have similarly indepent PCI busses.

http://www.amd.com/us-en/Processors/TechnicalResources/0,,30_182_739_9004,00.html

As far as ethernet, fireware, and so on... in PC-land I know these are very often integrated into chipsets and not connected to any PCI bus at all. I thought Apple was doing the same thing, seeing as how it is both more cost effective and faster.

 

[dguisinger]

dguisinger:


Perhaps that was true once, but its not anymore. Apple's G5 PCI-X chip appears to be an AMD chip (AMD-8131) which sprouts no less that 3 PCI/PCI-X busses which are totally independent and connected, through the chip, to HT and from there into the system RAM through the northbridge (which is on-CPU for an AMD chip). The Sun machines I've speced recently have similarly indepent PCI busses.

http://www.amd.com/us-en/Processors/TechnicalResources/0,,30_182_739_9004,00.html

As far as ethernet, fireware, and so on... in PC-land I know these are very often integrated into chipsets and not connected to any PCI bus at all. I thought Apple was doing the same thing, seeing as how it is both more cost effective and faster.

Umm, you do realize that the PCI bus exists within the Chipsets do you not? Most ethernet designs, like the ones on the X-serve are hooked into the internal PCI chipset, INTO the PCI bus. Want to know why? PCI is more than just sending data, its a method of configuration, a method of bus mastering, dma control, etc. HT doesn't provide that. HT provides a direct link from one point to another, its not designed to be a bus, its designed to be a point to point connection. The media kept talking about how HT was to be AMD's PCI replacement, going up against Intel's PCI Express (then known under a different name), and its funny, people beleived them. AMD was even quoted saying it was not designed to be a perhipheral expansion bus!

There are some systems that do support independent busses, HOWEVER: The PCI bus for example on x86 systems has a standard IO range. Putting a second bus on the same machine thats independent means any 3rd party OS will not detect it without being told where it is. Apple has a benifit in this situation because they control the platform, but not all architectures are as easily modifiable.

Have you read the PCI spec front to back? I haven't read every page of it, but the fact remains I have worked on kernel level PCI code. I have a book sitting on the shelf behind me that all it talks about is PCI... I have a fair deal of knowledge how PCI and PCI bridges / bus controllers work. Most devices will not ever connect directly into HT because it doesn't provide most of the functions devices need to actually communicate with the OS.

HT is like a wire.... PCI is the operator at the end of a TTD phone call.......it tells the PCI devices to configure how the OS wants them to..... As far as I can tell HT isn't configurable by the OS from what I've read, its just the line......a point to point serial protocol designed for higher front side bus speeds and to eliminate circuit trace complexity on the mother board. The OS still needs a standard interface for Plug-n-Play which PCI provides for detection, configuration, and operation.

 

[Mav451]

Yeah I remember...something along the lines of Hypertransport not competing with PCI Express, but working together (e.g. any of those Athlon 64 chipsets that will soon to be integrating PCI-E as a living testament to this).

A quick search found me this:
http://www.us.design-reuse.com/articles/article4199.html

Appropriately titled "How HyperTransport and PCI Express complement each other" 🙂

 

[ddtlm]

dguisinger:

There are some systems that do support independent busses, HOWEVER: The PCI bus for example on x86 systems has a standard IO range. Putting a second bus on the same machine thats independent means any 3rd party OS will not detect it without being told where it is.

What are you talking about? I'm talking about x86 machines with 3 PCI busses that I have handled with my own hands, no special configuration. They have full independent bandwidth. Lots of Opteron boards are like that. The Sun machines I speak of (V440 for example) also have full bandwidth, and the PCI busses aren't even hooked into the same chip on the system. I'm pretty sure some Itanium systems from HP have 6 or more PCI-X busses hooked to totally separate chips.

Have you read the PCI spec front to back? I haven't read every page of it, but the fact remains I have worked on kernel level PCI code. I have a book sitting on the shelf behind me that all it talks about is PCI... I have a fair deal of knowledge how PCI and PCI bridges / bus controllers work.

That's good, but your still making incorrect claims, such as:

HOWEVER: Most multi-bus systems actually combine all the buses with PCI-PCI bridges, therefore grouping some bottlenecks, but ultimately access to the main CPU/memory still remains a bottle neck of the main PCI bus.

Wrong, but don't ask me how to resolve the conflicts of the real world with the PCI spec cause I haven't a clue.

 

[melgross]

PCI-PCI Express

Guys, there's no point in arguing the fine points. It's fairly simple overall.

The PCI bus is finished. That's all that matters for Apple. PCI-X was invented as a cheaper lower technology competitor to the Intel invented Express bus. The only advantage to PCI-X is that as it is related to PCI 2, it is easy to engineer, and costs less. It has about twice the bandwidth and has been implemented by server companies who couldn't wait for Express to come out. Also, server companies are conservative, and wanted to go with something that wasn't re-engineered from scratch, which Express is.

Apple had no choice but to go with X because Express wasn't ready. It's just now coming out.

The industry estimates are that by January, 50% of all new Pc's will come with Express. However, a Pc being, after all, a Pc, a large number of those units will still have PCI 2.2 slots as well, ala PCI/ISA. Several mobo makers have also shown Express mobo's with 8x AGP on the board as well, though the performance is poor. It's just for compatibility.

Express ver. 1 is four times faster than PCI 2.2 about 1GB sec, vs. 266MB sec. Ver 2 arriving in 2006 will be about 2GB sec.

PCI-X is a dead end. Apple must shift to Express. The question is when. I'm hoping that January will be that time. Intel has shown their cards, and there were about a dozen at the show in, I forget now, I think Taiwan, last month.

If Apple doesn't do this soon, then they will suffer not being in step. There have been few X cards issued because most X makers have, as I've said, been Server companies who don't use most cards. What little there is will trickle to a halt sometime in 2005. Apple has to be at the front of this curve, not behind it. Whatever you may think of these busses, Apple has to be perceived as having the most muscle, and the greatest capabilities.

Having Express will help them to achieve that goal.

 

[faustofernos]

Read this alound (with Comic Book Guys' Voice)

If you read this alound as the comic book guy (from the Simpsons) its hilarious! ha ha ha ha...

Umm, you do realize that the PCI bus exists within the Chipsets do you not? Most ethernet designs, like the ones on the X-serve are hooked into the internal PCI chipset, INTO the PCI bus. Want to know why? PCI is more than just sending data, its a method of configuration, a method of bus mastering, dma control, etc. HT doesn't provide that. HT provides a direct link from one point to another, its not designed to be a bus, its designed to be a point to point connection. The media kept talking about how HT was to be AMD's PCI replacement, going up against Intel's PCI Express (then known under a different name), and its funny, people beleived them. AMD was even quoted saying it was not designed to be a perhipheral expansion bus!

There are some systems that do support independent busses, HOWEVER: The PCI bus for example on x86 systems has a standard IO range. Putting a second bus on the same machine thats independent means any 3rd party OS will not detect it without being told where it is. Apple has a benifit in this situation because they control the platform, but not all architectures are as easily modifiable.

Have you read the PCI spec front to back? I haven't read every page of it, but the fact remains I have worked on kernel level PCI code. I have a book sitting on the shelf behind me that all it talks about is PCI... I have a fair deal of knowledge how PCI and PCI bridges / bus controllers work. Most devices will not ever connect directly into HT because it doesn't provide most of the functions devices need to actually communicate with the OS.

HT is like a wire.... PCI is the operator at the end of a TTD phone call.......it tells the PCI devices to configure how the OS wants them to..... As far as I can tell HT isn't configurable by the OS from what I've read, its just the line......a point to point serial protocol designed for higher front side bus speeds and to eliminate circuit trace complexity on the mother board. The OS still needs a standard interface for Plug-n-Play which PCI provides for detection, configuration, and operation.

 

[ktlx]

You're joking me right? That picture is a diagram of the overall I/O connections in the X-serve--not specifically the PCI bus. This is why it shows the 2 G5's, memory, and FSB linked together (this is called the Northbridge) at the top.

At the bottom, is the Southbridge and its respective, connected devices. The PCI bus is part of the Southbridge--where the devices are connected to it: Hard drives (SATA or PATA, it doesn't matter); USB/FW800; and the Optical drives

I'm not sure how onboard Ethernet works, but it seems it has an "independent" bus for it on the XServe, so we might be able to factor it out of the equation (in terms of sharing the PCI bus bandwidth).

Did you even bother to read the page I referenced? Either you did not or you did not understand what it is saying.

 

[Mav451]

You know, for a post that started off telling someone else they did not know what they were talking about, it would help if you knew what you were talking about. None of the devices mentioned are on a shared PCI bus according to Apple's architecture diagram. Please see http://www.apple.com/xserve/architecture.html for more information.

Actually I did. This time, I'll even circle the picture for you.
(top red square = northbridge, lower red square = southbridge)
(blue circles = devices connected to southbridge, via PCI bus and talk to the devices in the Northbridge by HyperTrasnport--think of it as a wire between the Northbridge and Southbridge)

Upon further inspection, at least by the diagram, it seems the Ethernet and PCI-X are independent of the PCI bus (as they are not connected to the HyperTransport at the bottom).

To answer your question, ALL of the devices he mentioned, except the Gigabit Ethernet, are funneled through the PCI bus:

As it is right now, PCI is overwealmed with data. Look at the XServe. 3 Serial ATA controllers running at 150MB/sec. 2 Gigabit ethernet controllers. An optional Fibre Channel card...lets not forget USB2 and FireWire 800.

As I indicated on my picture, the SATA and USB2/FW800 are both linked to the HT (and consequently are part of the PCI bus, run BY the southbridge). The Fiber Channel cards, it seems, are normal PCI cards, NOT PCI-X cards, so they do not get the advantage of running independent of the PCI bus (and hence, are part of the latency or "wait" situation).

 

[shawnce]

Guys why are you working from an artitist rendering and market speak? Go to the real documentation (well as real as Apple publicly releases).

http://developer.apple.com/documentation/Hardware/Developer_Notes/Macintosh_CPUs-G5/PowerMacG5/

In particular the chapters on block diagram and K2 I/O Controller.

Note the following diagram contained in that documentation...

Also such data exists for the Xserve as well (rather close to the current G5s)...

http://developer.apple.com/documentation/Hardware/Developer_Notes/Servers/XserveG5/index.html

 

[Mav451]

Good god...that's quite a find.

 

[shawnce]

FYI by my math all of the IO devices connected to the K2 I/O controller (south bridge) cannot peak much above 800 MBps (megabytes per second). The HT bus feeding the K2 can support up to 1600 MBps (full duplex).

Also note that the K2 internally appears to simulate many PCI buses (not one big shared PCI bus) with PCI bridges off of those to interface to the i2s, SATA, etc. buses supported (as seen with IOReg). It does expose one PCI 64b/33MHz bus for attaching the USB controller, airport card, and boot ROM.

Anyway I do not believe that all devices attached to the K2 I/O controller share a single PCI bus internally but the K2 supports many internal PCI buses (possibly simulated for the benefit of software drivers) all bridged off of the one HT bus attaching it to the system. An HT bus with enough bandwidth to cover any peak bandwidth loads. The chip set is well balanced with little to no bottlenecks designed into it.

 

[stuepfnick]

But it seems to suffice

The 1.6 GBs throuput seems to suffice for all that stuff.

450 MBs for 3 HDs
050 MBs for an extreme optical drive
100 MBs FW800
100 MBs 2x FW400
150 MBs 3x USB 2.0
001 MBs bluetooth
005 MBs Airport Extreme
120 MBs Gigabit Ethernet
010 MBs Audio stuff

The PCI slots are seperated, so that makes totalle 986 MBs throughput! The maximum is 800 MBs in one direction. And you will never ever in any way get full usage of all this stuff at the same time! That would mean max. possible read speed of all drives, of all I/O devices, etc. This is really impossible in any way of usage you can think of.
So can't see any bottleneck there in any way...

 

[shawnce]

Good god...that's quite a find.

Apple has always provided documentation such as this on their developer site (no registration needed). 🙂

http://developer.apple.com/documentation/Hardware/AppleHardware-date.html

Note the "All Hardware Products" at the bottom to see some real history and just how far they have come.

 

[stuepfnick]

The 1.6 GBs throuput seems to suffice for all that stuff.

450 MBs for 3 HDs
050 MBs for an extreme optical drive
100 MBs FW800
100 MBs 2x FW400
150 MBs 3x USB 2.0
001 MBs bluetooth
005 MBs Airport Extreme
120 MBs Gigabit Ethernet
010 MBs Audio stuff

The PCI slots are seperated, so that makes totalle 986 MBs throughput! The maximum is 800 MBs in one direction. And you will never ever in any way get full usage of all this stuff at the same time! That would mean max. possible read speed of all drives, of all I/O devices, etc. This is really impossible in any way of usage you can think of.
So can't see any bottleneck there in any way...

Oh sorry, the Ethernet is also seperated, so that could actually only get to the limit, when all I/O connectors run at full speed in the same direction, which is 100% impossible.

 

[gossas]

Isn't this getting a bit retentive.

There's obviously naff all going on as people are now arguing over diagramatical and mathematical theoretical values. Bottom line, until someone can guide me through using Macromedia suite on my new machine and I subjectively believe that everything runs faster, then why should I believe it's faster. On paper all new machines are faster or slower by design, benchmarks quantify theory and real world tests are subjective and qualitative. No test has any bearing on my enjoyment of my new machine.

 

[fregedegpo]

sound issues....

My big wish is that the sound issues will be solved that came from the power supply corrupting the anolog audio outs. I bought a dual2 G5 for myself and the problem was aweful - luckily the store agreed to return the unit - and then I bought one for my work and found the same problem. 2 out of 2 is not good!

I need a new cpu so badly, as I use Logic on my dual500 G4 and the new plugins can barely make it on these procs. But I don't want to buy a computer that has serious sound problems. Does anybody know about the dual 2.5 G5, or even these revised dual 2 G5s?

Thank you folks, I hope somebody has some info.... 🙂

 

[nuckinfutz]

My big wish is that the sound issues will be solved that came from the power supply corrupting the anolog audio outs. I bought a dual2 G5 for myself and the problem was aweful - luckily the store agreed to return the unit - and then I bought one for my work and found the same problem. 2 out of 2 is not good!

I need a new cpu so badly, as I use Logic on my dual500 G4 and the new plugins can barely make it on these procs. But I don't want to buy a computer that has serious sound problems. Does anybody know about the dual 2.5 G5, or even these revised dual 2 G5s?

Thank you folks, I hope somebody has some info.... 🙂

You're "never" going to want to use the audio capabilities of the computer(hardware wise). After getting Logic you'll need to investigate a good audio interface. PCI or FW or USB, Core Audio was meant to handle these quite well.

 

[gerardrj]

More numbers

Here's another table of G5 optimized CineBench numbers for the 2.0 vs 2.5 hz models:

1st gen Dual G5 @ 2GHz; 1.5GB RAM; stock Radeon 9600w/64MB
Supplied 2x2.5 numbers in parenthesis ()
calculated percent change in brackets []

Rendering (Single CPU): 287 (356) [+24%] CB-CPU
Rendering (Multiple CPU): 510 (633) [+24%] CB-CPU
Multiprocessor Speedup: 1.78 (1.78) [0%]

Shading (CINEMA 4D) : 278 (335) [+20%] CB-GFX
Shading (OpenGL Software Lighting) : 776 (995) [+28%] CB-GFX
Shading (OpenGL Hardware Lighting) : 1507 (1794) [+19%] CB-GFX
OpenGL Speedup: 5.43 (5.36) [-2%]

Apparently the 2.5Ghz machine achieves little to no performance gain because of the smaller process size, the overall difference in performance is about 25%, sometimes a little higher, sometimes a little lower but it equates solely to clock speed increase.

 

[eric_n_dfw]

Apparently the 2.5Ghz machine achieves little to no performance gain because of the smaller process size, the overall difference in performance is about 25%, sometimes a little higher, sometimes a little lower but it equates solely to clock speed increase.

Forgive my ignorance, but why would the smaller process size in and of itself increase performace? I thought the point of the smalller size was to shorten the distances the electrons need to travel, thus allowing the higher clock speeds.

 

[veggyrites]

it takes two

didn't the 30" use two GPU's to run, on the keynote Steve showed us half a screen with only one GPU.

that is all 😕

 

[DWKlink]

didn't the 30" use two GPU's to run, on the keynote Steve showed us half a screen with only one GPU.

that is all 😕

I believe that its only one card. The half screen was a limitation of the DVI interface. A single DVI connection cannot carry all the information needed to drive the monitor at full rez. So they developed Dual DVI - basically two DVI paths on one cable running in parallel as I understand it - to drive the monitor. And the 6800 includes 2 of these dual DVI ports to drive up to 2 30" displays at full rez. But I think that the card itself only includes one GPU.

 

[veggyrites]

oh

ok , that is better

 

[eric67]

indeed, the CineBench version were mixed

Here's another table of G5 optimized CineBench numbers for the 2.0 vs 2.5 hz models:

1st gen Dual G5 @ 2GHz; 1.5GB RAM; stock Radeon 9600w/64MB
Supplied 2x2.5 numbers in parenthesis ()
calculated percent change in brackets []

Rendering (Single CPU): 287 (356) [+24%] CB-CPU
Rendering (Multiple CPU): 510 (633) [+24%] CB-CPU
Multiprocessor Speedup: 1.78 (1.78) [0%]

Shading (CINEMA 4D) : 278 (335) [+20%] CB-GFX
Shading (OpenGL Software Lighting) : 776 (995) [+28%] CB-GFX
Shading (OpenGL Hardware Lighting) : 1507 (1794) [+19%] CB-GFX
OpenGL Speedup: 5.43 (5.36) [-2%]

Apparently the 2.5Ghz machine achieves little to no performance gain because of the smaller process size, the overall difference in performance is about 25%, sometimes a little higher, sometimes a little lower but it equates solely to clock speed increase.

good info.
hardmac.com is also providing very similar resutls, one should have a look.
http://www.hardmac.com/niouzcontenu.php?date=2004-07-05#2434

 

[WinX]

It is obvious you don't understand what PCI Express is. PCI Express is (AFAIK) a 4-wire RX/TX pair capable of pushing in serial more bandwidth than a normal PCI slot, and if I remember correctly it is a jump from 133MB/sec to 150MB. Someone can correct me on that if I'm wrong.

Correct you? Easy. A 1x PCI Express is clocked at 2.5 Gigabits/sec...

On standard PCI, ALL SLOTS SHARE the 133MB/sec bus!

On an antiquated decade-old PC, maybe. What you don't seem to understand is that a modern Southbridge chip can implement a multitude of INDEPENDENT PCI buses.

As it is right now, PCI is overwealmed [sic] with data. Look at the XServe. 3 Serial ATA controllers running at 150MB/sec. 2 Gigabit ethernet controllers. An optional Fibre Channel card...lets not forget USB2 and FireWire 800. All of this is funnelled into the SAME PCI BUS.

Um, the operative word, even on a G4 Xserve, is INDEPENDENT buses. Serial ATA disks, Firewire and USB interfaces DO NOT need to communicate with each other, and thus DO NOT need to SHARE a bus.
The computer-side end point of an I/O operation will typically be RAM -- e.g. via a DMA controller -- or a CPU. The I/O links are thus conceptually point-to-point; Apple's G5-based machines implement that point-to-point paradigm using a combination of hardware -- e.g. the G5's Apple-designed and IBM-manufactured "Northbridge" -- and software -- multiplexing of logical point-to-point links over a single 800 Megabytes/sec multiplxed Hypertransport channel to the K2 controller.

We should thank stuepfnick for showing in a previous post that it would be next to impossible to overwhelm an Xserve G5's 800 MB/s HT channel in real-world conditions...

I for one, am under strong beleif, that a new XServe will be announced in the August / September time frame with PCI Express, as it can take advantage of the PCI Express throughput the most with all the integrated devices in the server.

Um, the 2 Gigabytes/sec throughput offered by the G5 Xserve's PCI-X slots is sufficient to comfortably support even cards requiring high throughputs. Fiberchannel interfaces run at 1.06 to 2.12 Gigabits/sec. Infiniband runs at 10 Gigabits/sec with 8b/10b encoding, thus actual peak payload throughput is more like 8 Gigabits/sec.

Have you read the PCI spec front to back? I haven't read every page of it, but the fact remains I have worked on kernel level PCI code.

Um, PCI semantics do not necessarily need a physical parallel "PCI" bus. The PCI protocol can be implemented as a layer above a serial physical layer, like PCI-Express or Hypertransport. People unfamiliar with modern hardware design concepts or point-to-point traffic patterns apparently don't realize that PCI driver software wouldn't be able to tell the difference.

 

[g4cubed]

I believe that its only one card. The half screen was a limitation of the DVI interface. A single DVI connection cannot carry all the information needed to drive the monitor at full rez. So they developed Dual DVI - basically two DVI paths on one cable running in parallel as I understand it - to drive the monitor. And the 6800 includes 2 of these dual DVI ports to drive up to 2 30" displays at full rez. But I think that the card itself only includes one GPU.

dual link DVI passes along twice the information of standard DVI along the same cable by using all 24 pins of the connector instead of just 12. All this graphics power comes at a space price as well—the card itself is so big that it takes up the space of two PCI cards