yeah, Northwestern University Bookstore doesn't sell computers...Oh yeah, they don't have to. Their books cost the same as computers.
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PowerMac G5's Arriving...
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Here too...if I took the money I spent on books these past two years of college, I'd be able to afford *at least* a 1.6 GHz G5...gotta love college life.
OMG- I need to run away!
Bought an iPod in Dec 2002...Bought a 12" PB in Feb...now all this talk of G5s in stock not reserved is getting me all crazy with the thought of going to the Apple Store, breaking out the checkbook and getting a 1.6 and a 20" cinema display...I need to stop looking at this forum and run away just so I can not have such crazy thoughts of another Mac in just one year....Aiiieeeee!
Bought an iPod in Dec 2002...Bought a 12" PB in Feb...now all this talk of G5s in stock not reserved is getting me all crazy with the thought of going to the Apple Store, breaking out the checkbook and getting a 1.6 and a 20" cinema display...I need to stop looking at this forum and run away just so I can not have such crazy thoughts of another Mac in just one year....Aiiieeeee!
Correction....
The bandwith (of a 1.8ghz) should be 900Mhz unless it is slowed by the speed of the ram.
I hope to get my Dual G5 early; I'm an educator, and have already ordered my dualie. I believe in about a year this school will have a modest amount of switchers, or plain miserable pc users that will endure pain just to not swallow their pride.
Fine by me.
The bandwith (of a 1.8ghz) should be 900Mhz unless it is slowed by the speed of the ram.
I hope to get my Dual G5 early; I'm an educator, and have already ordered my dualie. I believe in about a year this school will have a modest amount of switchers, or plain miserable pc users that will endure pain just to not swallow their pride.
Fine by me.
Originally posted by tychay
Too late, if you ever bothered to look at the Apple Quicktime VR of it, you see that that you can remove the aluminum door and leave the clear-plastic panel on (for airflow reasons).
I imagine a lot of people will be leaving their Mac like that in the coming months.
Take care,
terry
Does the machine still meet radio suppression requirements with the aluminum door off, though.
Internal bandwidth data
Actually, the speeds depend on the computer model and the part of the system at which you are looking. Time for the techie part!
The G5 has four (or five) main chips. The two obvious chips are the CPU (one or two) and the Apple-designed IBM-produced controller chip (U3). For each chip, there are two one-way links between the U3 and the processor. Each of the two U3-processor links flow in only one direction (either to or from the processor), and carries 32-bits at a time at half the processor speed (i.e. 800 MHz on 1.6GHz system).
The U3 then connects to a bridge chip that provides for the PCI/PCI-X slots. The bridge chip connects to U3 with a 16-bit HyperTransport connection, allowing data transfers of up to 3.2GBps (again, giga-bytes). The type of slot depends on the model purchased:
Actually, the speeds depend on the computer model and the part of the system at which you are looking. Time for the techie part!
The G5 has four (or five) main chips. The two obvious chips are the CPU (one or two) and the Apple-designed IBM-produced controller chip (U3). For each chip, there are two one-way links between the U3 and the processor. Each of the two U3-processor links flow in only one direction (either to or from the processor), and carries 32-bits at a time at half the processor speed (i.e. 800 MHz on 1.6GHz system).
- The U3 also connects directly to RAM. The connection runs at either 333 MHz (for the 1.6GHz model) or 400 MHz (for the 1.8GHz and dual-2GHz models), carrying 64 bits at a time. Also, the bus runs at double the data rate, requiring DDR SDRAM (installed in pairs).
- The U3 also connects directly to the AGP port, providing the graphics card with 2.1GBps (that's giga-BYTES per second).
The U3 then connects to a bridge chip that provides for the PCI/PCI-X slots. The bridge chip connects to U3 with a 16-bit HyperTransport connection, allowing data transfers of up to 3.2GBps (again, giga-bytes). The type of slot depends on the model purchased:
- On the 1.6GHz system, all slots are 33MHz PCI slots.
- On the 1.8GHz and dual-2GHz systems, one slot provides up to 133MHz PCI-X. The other two slots provide up to 100MHz PCI. The single-133 and dual-100 slots scale down to the speed of the lowest card.
[/list=a]
The bridge chip then connects to the controller chip (K2) that connects to all of the interface ports. It is connected to the bridge chip with a 8-bit 1.6GBps HyperTransport connection.- Separate 12MBps USB connections are provided to the internal modem (if purchased) and the Bluetooth card (if purchased).
- Two Serial ATA buses, running at 1.5GBps (giga-bits) each, provide connections for the two internal hard drives. NOTE: Serial ATA to Parallel ATA adaptors are not supported in the G5
- A direct (proprietary?) connection is made to the power controller (PMU99)
- A direct (proprietary?) connection is made to the FireWire controller, which provides two 400MBps ports and one 800Mbps port.
- An I2S (inter-IC sound) connection is provided for the audio circuitry. That drives the line connections (in/out), the headphone jack, and the optical connections
- A direct connection is made to the built-in Ethernet port
- A 33MHz PCI bus is provided for the following devices:
- Boot ROM
- AirPort Extreme card
- USB controller, which provides three USB ports (480 Mbps) and the USB connection to the AGP slot.
[/list=1]
As you can see, you can have a large amount of data running around. Luckily, multiple streams of data can run around without knowing about each other. For example, the video card can be accessing memory while the processor is interacting with the PCI slot, and neither data stream will have to interact as they move through the U3 controller chip.
For more information, see the following resources:- The Power Mac G5 Developer Note.
- Technical Note 86416.
- Recording of WWDC session #502, "Power Macintosh G5 Architectural Overview", available at the ADC Member site. Go to "View ADC TV".
Re: Correction....
Umm, no. The bandwidth you are talking about is the bandwidth between the CPU and the Apple system controller ("Northbridge" in PC terms). The bandwidth I was talking about is between the Apple system controller and the memory. They do not have to be the same. (Believe me, a lot of PC users confuse this, just because they have the latest P4 with an 800 MHz FSB doesn't mean their memory is going at 800Mhz!)
In fact, DDR memory right now doesn't go faster than 200Mhz (PC3200). This is a small correction to the previous post. The actual computation is that the RAM is 200Mhz but you are sending data on the rise and fall of every clock (DDR) and you are sending through two sticks independently (dual channel): 200Mhz * 2 * 2 * 64bits/8(bits/byte) = 6.4GB/s, or an effective bandwidth of 800Mhz, or "an entire DVD in a second" as Jobs put it*.
The 1.6Ghz G5 uses PC2700 put down in pairs (dual channel) so it's RAM has an effective bandwidth of 666Mhz. I was pointing that the gap between the pairs of bays made sense when you remember that the RAM is dual-channel.
The previous post claimed 400Mhz and confused dual channel with double-data rate--but his math is correct so it's all good.
As he notes, since HyperTransport is a point-to-point bus, there is no contention. So even if the RAM is "not fast enough" for your FSB, doesn't mean that the CPU couldn't instead be querying the PCI and the AGP card using the RAM or whatever. (Or one processor can be using the hard drive buffer while the other grabs from the RAM in your 2x2Ghz G5). There are no bottlenecks in this, so comparisons with the G4 bandwidth limitations are not apt.
Take care,
terry
* This is interesting to think about though incorrect. There are various latencies in RAM addressing and access which would prevent this.
Umm, no. The bandwidth you are talking about is the bandwidth between the CPU and the Apple system controller ("Northbridge" in PC terms). The bandwidth I was talking about is between the Apple system controller and the memory. They do not have to be the same. (Believe me, a lot of PC users confuse this, just because they have the latest P4 with an 800 MHz FSB doesn't mean their memory is going at 800Mhz!)
In fact, DDR memory right now doesn't go faster than 200Mhz (PC3200). This is a small correction to the previous post. The actual computation is that the RAM is 200Mhz but you are sending data on the rise and fall of every clock (DDR) and you are sending through two sticks independently (dual channel): 200Mhz * 2 * 2 * 64bits/8(bits/byte) = 6.4GB/s, or an effective bandwidth of 800Mhz, or "an entire DVD in a second" as Jobs put it*.
The 1.6Ghz G5 uses PC2700 put down in pairs (dual channel) so it's RAM has an effective bandwidth of 666Mhz. I was pointing that the gap between the pairs of bays made sense when you remember that the RAM is dual-channel.
The previous post claimed 400Mhz and confused dual channel with double-data rate--but his math is correct so it's all good.
As he notes, since HyperTransport is a point-to-point bus, there is no contention. So even if the RAM is "not fast enough" for your FSB, doesn't mean that the CPU couldn't instead be querying the PCI and the AGP card using the RAM or whatever. (Or one processor can be using the hard drive buffer while the other grabs from the RAM in your 2x2Ghz G5). There are no bottlenecks in this, so comparisons with the G4 bandwidth limitations are not apt.
Take care,
terry
* This is interesting to think about though incorrect. There are various latencies in RAM addressing and access which would prevent this.
Re: Re: GOT 'EM
All our prices are the same as on apple's education site (recently reduced), but only UW faculty/students can purchase from the store.
Good Vs. Evil ?
Now, let us not compare evil things with good ones...
Originally posted by KREX725
It looks so clean! It reminds me of the inside of the Death Star.
I'm in love!
Now, let us not compare evil things with good ones...
Re: Internal bandwidth data
Slight confusion here I think. Each DDR400 RAM module is clocked at 200 MHz. Data is accessed on both the up and down of the clock, hence "DDR"; which means the speed of each RAM module is actually 400 MHz at 64 bits per cycle. Additionally, RAM modules are paired and each pair is accessed simultaneously--so two 64-bit chunks are read at each 400 MHz cycle. That means 128 bits every 1/400 sec. This is equivalent to 64 bits every 1/800 sec, which is why it is called "800 MHz effective bandwidth".
Slight confusion here I think. Each DDR400 RAM module is clocked at 200 MHz. Data is accessed on both the up and down of the clock, hence "DDR"; which means the speed of each RAM module is actually 400 MHz at 64 bits per cycle. Additionally, RAM modules are paired and each pair is accessed simultaneously--so two 64-bit chunks are read at each 400 MHz cycle. That means 128 bits every 1/400 sec. This is equivalent to 64 bits every 1/800 sec, which is why it is called "800 MHz effective bandwidth".
Highly unlikely, and the interference caused might annoy some people. The 1.6GHz model will definitely cause interference in the TV band as well as space-to-Earth communications and the 1.8GHz model would cause interference in cellular and possibly amateur radio bands. And that's just the processor and the bus, who knows what frequencies other things inside the case are operating on.
Re: Re: Internal bandwidth data
That's correct, and I apologize for the earlier confusion. There are many places where I glossed over things, just to make it easier to convey. For example, Apples controller chip (the U3) connects to the processor using HyperTransport, but before it reaches the processor it is converted from a HyperTransport connection to something the processor can handle.
I could see a month-long set of classes coming from all of this! Learn the inner workings of the G5 in one month! (After spending 4 years learning the prerequisite Electrical Engineering, Physics, etc.)
That's correct, and I apologize for the earlier confusion. There are many places where I glossed over things, just to make it easier to convey. For example, Apples controller chip (the U3) connects to the processor using HyperTransport, but before it reaches the processor it is converted from a HyperTransport connection to something the processor can handle.
I could see a month-long set of classes coming from all of this! Learn the inner workings of the G5 in one month! (After spending 4 years learning the prerequisite Electrical Engineering, Physics, etc.)
When I look at the stanford bookstore website, I can't really find ouy clearly if it's only for academic and students to buy. The websites states that there are 'great' deals for Stanford students and educators, but it doesn't exactly say that the computer store is open to the public.
Any thoughts ideas ?
Any thoughts ideas ?
stanford store
It would be really interesting if our stanford correspondents could keep us uptodate with how quickly the boxes are shifting, to give us a good indication of whether these models, after the initial pre-ordered frenzy, are going to fly!
Ta
It would be really interesting if our stanford correspondents could keep us uptodate with how quickly the boxes are shifting, to give us a good indication of whether these models, after the initial pre-ordered frenzy, are going to fly!
Ta
Re: Re: Re: Internal bandwidth data
Apparently Apple refers to the bus as the Apple Processor Interconnect; IBM has its own over-branded name for the same thing (I forget exactly what it is, though). In any case I guess it is kind of similar to HyperTransport, with two unidirectional 32-bit buses, but I'm not sure if HT transmits address information like the API does. Maybe someone who knows more about HyperTransport and the API can educate us here.
HTH
WM
No, it doesn't.
Apparently Apple refers to the bus as the Apple Processor Interconnect; IBM has its own over-branded name for the same thing (I forget exactly what it is, though). In any case I guess it is kind of similar to HyperTransport, with two unidirectional 32-bit buses, but I'm not sure if HT transmits address information like the API does. Maybe someone who knows more about HyperTransport and the API can educate us here.
HTH
WM
Apple Processor Interface / HyperTransport
Let me quote my source for this: "IBM Joins HyperTransport Consortium". Mac Rumors. 11 August 2003. Ed. arn. 21 August 2003 <https://www.macrumors.com/pages/2003/08/20030811144341.shtml>.
That's where I got my information. However, the article was a bit inaccurate, since the "bridge chip" to which they are referring is actually the controller chip. Oh, well!
Let me quote my source for this: "IBM Joins HyperTransport Consortium". Mac Rumors. 11 August 2003. Ed. arn. 21 August 2003 <https://www.macrumors.com/pages/2003/08/20030811144341.shtml>.
That's where I got my information. However, the article was a bit inaccurate, since the "bridge chip" to which they are referring is actually the controller chip. Oh, well!
Just ordered a Dual G5
Well, I just ordered a dual G5. I was going to wait till Panther shipped but I got some pretty interesting info from the salesman. He said "legaly" he can only tell me that my order will be shipped in 4-8 weeks, but he expects that I will recieve it much much sooner. Also I asked him about a free upgrade to Panther and he said that "legaly" he can't say anything but Apple always takes care of there customers. So I'll keep my fingers crossed.
Well, I just ordered a dual G5. I was going to wait till Panther shipped but I got some pretty interesting info from the salesman. He said "legaly" he can only tell me that my order will be shipped in 4-8 weeks, but he expects that I will recieve it much much sooner. Also I asked him about a free upgrade to Panther and he said that "legaly" he can't say anything but Apple always takes care of there customers. So I'll keep my fingers crossed.
Re: Apple Processor Interface / HyperTransport
HTH
WM
That's all true. To clarify: I was simply pointing out that your assertion that "Apple's controller chip (the U3) connects to the processor using HyperTransport, but before it reaches the processor it is converted from a HyperTransport connection to something the processor can handle" is inaccurate.
HTH
WM