Re: Re: Re: here's a question...
Originally posted by Rincewind42
Oddly enough, this is one of those strange issues =).
The current P4 uses a Quad-Pumped 133 Mhz bus (the previous generation used Quad-Pumped 100Mhz) that gives an effective rate of 533 (and previously 400) Mhz. Of course, this isn't as efficient as a 533Mhz Single-Pumped bus, but it does have the same peak theoretical bandwidth.
Why would you say that a quad pumped bus is less efficient than a 'single-pumped' bus (never heard that slang)??
As far as the system is concerned... all that matters is how many 'ticks' per second are available. If you have 533 Million ticks per second, you have 533 Million chances to do something since each clock tick is a signal to the system.
There are currently two ways to generate these ticks. You have a 'clock' (usually a quartz chip) that ticks off time.... tick, tick, tick. You can listen for each cycle generated and therefore get one tick per Hz, or you can listen to each cycle at different points and get multiple ticks per Hz.
On an old SDR Bus, say a 133MHz bus, the quartz clock ticks off 133 Million times per second.
On a 'quad-pumped' [QDR] bus, the quartz clock may still tick at 133MHz, but you use multiple point on each cycle to represent a 'tick'. this allows you more signals to do something. The beauty of DDR and QDR is that you don't have to push the clock speed up to make it do more things. Try running an SDR DIMM and see what happens at 533MHz... the electrons hop from one gate to another, it overheats....bad stuff.
So,.. this is how it actually works... think of a sine wave on a typical x,y graph...
The wave goes up, the wave goes down. For each cycle (Hz) it accends, peaks, decends, crosses x, decends, peaks(-), accends, crosses x... and so on, and so on.
With SDR, the 'tick' comes after a full cycle.
With DDR, the 'tick' comes when the signal crosses x=0... so, you get a 'tick' while decending to x=0 and a 'tick' while accending to x=0.
Now... how is this any less efficient than an SDR solution?
It is actually significantly MORE efficient as you can generate significantly higher effective 'clock rates' without actually raising the clock and buring out your components.
And another thing, If it isn't as efficient, how could it have [as you assert] the same bandwidth? As far as the rest of the system, the QDR subsystem is running at an effective 533MHz (in this example). The idea of doubling or quadrupling a clock rate in this manner doesn't require increased latency.
