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Sandybridge Speculations...
- Thread starter JesterJJZ
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There's no reason they can't do SB + discrete GPU with an Optimus like setup. However, I feel that they won't because they won't like the profit margin. Perhaps 13" will become Arrandale and always lag a generation behind. After seeing the Vaio Z pack arrandale plus the 330M I don't buy that the logic board either can't fit or be cooled in Apple's 13" chassis size.
PCIe 2.0 x8 + x8 was not surprisingly more than enough for a dual GPU setup.
DMI and the remaining lanes outside of those dedicated to the GPU were where P55 and its siblings failed when it came to providing bandwidth for USB 3.0 and SATA 6 Gbps at the same time.
Apple would have to sacrifice battery space to make room for the extra chip. Recall, in the Core ix solution, we have the CPU, GPU and ICH module. So that extra space has to come from somewhere. I have a feeling that or an MacBook Air SSD approach; which I doubt the later.
Also now have the option to turn off discrete and use IGP. This solution is not possible in the C2D implementations. Still, battery life will suffer overall at the cost of space as you point out.
If looking specifically for a Mac Pro that is loaded down with workload:
Because it will be 10-30% faster on many heavy duty workloads. Much faster than that on highly vectorizable code ( better vector instructions than what SSE has provided. )
If have a Mac Pro that commonly runs at 10% utliization levels.... they don't really need the extra headroom.
Wow!
an Intel Core i7-2600K Sandybridge running at 5GHz + on air cooling
http://www.hardocp.com/image.html?image=MTI4ODEyNDMyM2RzUU1JdTlvc2tfMV8xX2wuanBn
an Intel Core i7-2600K Sandybridge running at 5GHz + on air cooling
http://www.hardocp.com/image.html?image=MTI4ODEyNDMyM2RzUU1JdTlvc2tfMV8xX2wuanBn
0.98V? Something is wrong there.... can't be that low and have a stable clock at 5GHz.... perhaps 1.2V
Nice spy. Even 1.2 at 5.0 GHz sounds wonky. That's around stock voltage. If the K's overclock that well and there's no workaround for the bclk lock on these Intel will be bending people over barrels for K prices.
Surprisingly, K prices are stable on the i5 and i7 front. It's the X prices that people have to bend over for.
In any case, yes you are right, even at 1.2V it looks fake.
Clicky
It is fake... Adobe Photoshop 6... nice try I'd say.
Sony uses some impressive stunts to make the VAIO Z
Intel seems to be having LGA 2011 appear on 22nm Ivy Bridge goodness
We might see:
20MB L3 cache
Octocore @3.6GHz
Quad Channel (Confirmed)
40 PCI-E 3.0 lanes (Confirmed)
In reality we will only see x36 PCIe 3.0 lanes. The other x4 will be dedicated to the DMI.
In any case, the 20MB L3, seems a bit steep. Maybe 12MB for the Quads, 16MB for the Hexs.
QPI would be used to communicate with the IOH and that steps down to the PCH/SB over DMI.
but isn't 22nm less than 50% of 32nm? (I'm assuming 22•22 vs. 32•32)
therefore they could double it?
Forgot about that... thank you for the reminder.
Scaling isn't linear to die size.
Currently Intel has a Hexacore operating at 3.33GHz with 12MB L3
Isn't it possible to hit 20MB L3 and eight cores on the very high end with 22nm?
Possibly even 10 or 12-core in the high-end as Sandy Bridge is expected to have 8-core variant (for SP and DP market, not just MP).
Gainestown and Westmere have 2MB of L3 cache per core so if that is followed, then it's 16MB for 8-core but according to this (not reliable at all but just linking it), there will be 2.5MB of L3 cache per core, thus 20MB for 8-core.
More specifically, scaling isn't quadrilinear to die size either. It neither reliably follows the process size or its square. While the gate length minimum is the advertised process size, the gate width is not necessarily directly proportional, and this is true for a multitude of other things like vias and such.
You spiked my interest, go on. (I know nothing in the die is linear or in direct increase with increased space)
That's the extent of my knowledge since I am not involved in digital CMOS design. Lithography will determine the smallest dimension you can reliably create, but that doesn't mean other concerns like mechanical stress and electromigration won't dictate things like line width, length, interconnects, etc. There may be some rule of thumb out there for how much more transistors per sq/mm you can fit with each process shrink, but I've never seen one.
Lightpeak is coming soon according to this article:
http://news.cnet.com/8301-13924_3-20021658-64.html
http://news.cnet.com/8301-13924_3-20021658-64.html
That fights again what Intel said in IDF. IIRC availability was late 2011 and first computers with LP will appear in 2012. Although I wouldn't mind to see it earlier
That fights again what Intel said in IDF. IIRC availability was late 2011 and first computers with LP will appear in 2012. Although I wouldn't mind to see it earlier
"The Intel fellow also made clear the release plans and noted that Light Peak would only become available to component makers in late 2010. Actual shipping PCs should be ready earlier in 2011."
http://www.electronista.com/articles/10/04/14/intel.suspects.light.peak.will.take.over/
that's what internet said when I asked it. That was at beijing intel dev forum.