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There are various elements of different measurements within the chip - but the actual transistor gate being an accurate measurement of the process nm hasn't been true since 1994.

The chip makers would make improvements to the process, and have measurable improvements in power usage, and number of transistors that could be packed within a certain space, so they would then declare this a new process, and reduce the "nm" to show they were ahead of the competing chip makers.
lately some have been using new terms - like TSMC using N4P & N4X for new processes that are still part of the "5nm" family, but offer improvements in speed (11% for N4P) & power usage (22% reduction for N4P) - it's compatible with earlier 5nm designs, so doesn't require a whole new design from the company that wants the chips produced. "The N4, N4P, and N4X nodes are design rules-compatible with 5nm technology for easy design migration" - https://www.tsmc.com/english/dedicatedFoundry/technology/platform_HPC_tech_advancedTech

When they introduced their N3 "3nm" family, it was different from the 5nm family, and requires a new design from the chip designer to be produced with the new process. Unfortunately it looks the next version of this is N3E and "N3E will not offer any direct migration path from N3, making N3 sort of a dead-end node for designers which is why TSMC expects most customers to utilize N3E instead." - so to take advantage, chip designs have to be modified from the initial N3 design that Apple used. They did know this in advance, and still wanted to be first with the new "3nm" process.
 
I was planning to jump into the 3nm with the N3E or the N3P process, with the M4 chip (2024) but maybe it is a good idea to wait a bit more if the first 2nm SoC are coming in 2025? I don’t know, I think my purchase will come conditioned by the ML capabilities and the in-device processing of the future Apple LLM.

Yeah, I know, I’m pursuing a carrot that I’ll never reach.
 
Erm... no. According to the IEEE, the "2 nm" node anticipated for 2025 refers to a transistor size ranging from 12 nm to 45 nm. Features smaller than 12 nm aren't expected any time in the foreseeable future:
The IEEE is the Institute of Electrical and Electronics Engineers, and a reliable source.
Wikipedia says 45 nm, which may be the most relevant for CPUs:
Edited to add: @oneMadRssn pointed out that the measures I cited above, such as "12 nm" and "45 nm", are technically the _gate_ sizes, which are smaller than the _entire_ transistor. Anyway, a feature 2 nm across would be 9 silicon atoms across, resulting in a device too unreliable to use at any temperature, even if manufacturing were perfect.
This is informative.
Strangely enough, I would have swallowed a lot of that without doing the actual math because it sounds like it might be right.
 
Cue all the "My new M3 Mac that I haven't bought yet is already out of date" comments.
My M3 Mac which I have yet to buy is already out of date!

Was thinking of getting a new Mac (to replace my current 15 y.o. iMac) after Christmas.... but maybe I should wait until the 2nm chip, just to make sure I see a difference. .... 👀
 
I’m holding off for the negative nanometer chips. The ones that will actually generate power when you use them and run infinitely fast and cool down the device the more they are used. /s
 
To build on some of the answers others have given, node procession as a numerical value really is a marketing exercise at this point. The underlying progression still generally refers to efficiency and to a lesser extent transistor count, but the technologies that get there aren't a simple shrinking anymore. Areas such as 3D packaging and all around the gate designs used to reduce leakage (and thus boost efficiency) are just some of the technologies involved.
While this isn’t entirely incorrect, I think the “it’s all marketing” explanations have been put out by intel and their benefactors as they haven’t been able to make progress in process shrinkage so getting people to think it’s all marketing is to their benefit. Transistor size leads to transistor density per die area, and that is continuing to scale in proportion to these “marketing” process names.
 
Bring it on my 15 Pro Max will be slow in 2025
Let's hope it's slow in 2025. That should mean the software team has incorporated massive new functionality, continuing to drive innovation (or everything went electron). The truth is Apple has plenty of experience incorporating software features in new OS's such that they balance slowing down older phones with new features being added. I wouldn't expect a 15 Pro Max to feel slow in 2025, but maybe a bit sluggish in 2026-27 and have plenty of new features but missing some of the latest and greatest stuff that the iPhone 18 can do.
 
What this article does not mention is that TSMC is actually behind Samsung and Intel in implementing next gen process features. These features are:
  • Gate-all-around field-effect transistors (GAAFETs). Samsung is already manufacturing chips with this feature and Intel (they call it RibbonFET) has it too but it's not in production yet.
  • Backside power delivery (the power to transistors is delivered from the back side of the substrate through the silicon as opposed to being delivered from the top as is the case now). Intel has demonstrated this feature and is expected to have it in their 20A and 18A processes.
 
It's not just Apple, but AMD, Nvidia, Qualcomm, so on and so forth. All of these vendors have custom ASIC designs and rely upon specific needs from TSMC to have their IP produced into end products.

With the US and Japan having restricted chip technologies to China and other nations with ties to China, Apple, AMD and all these big shops are expanding their Fab options to keep supply chains running globally. So you can expect Samsung to gain contracts as well, not just TSMC.

The TSMC Arizona plant is tentative to start operation Q2 2025, at the earliest.

Good article discussing the dual between TSMC and Samsung.

Article: https://www.trendforce.com/news/202...uencing-samsungs-advanced-packaging-strategy/

Samsung second fab in Texas 2h 2024 ahead of TSMC.

Here's the kicker: ‘`In November of this year, Samsung unveiled a new strategy called “GDP,” focusing on Gate-All-Around (GAA) transistor technology, DRAM, and 3.5D advanced packaging. The company has pledged to achieve a goal where more than half of its wafer foundry revenue comes from AI chip orders within five years.''

You can bet TSMC will do the same.

So, what is Apple doing with AI that would require TSMC to make them priority one when AMD and Nvidia are churning out massive AI products and ever expanding product lines moving forward that the largest vendors are demanding [Google, AWS, Microsoft, Oracle, Salesforce, IBM, Lenovo, etc]?

Apple just putting Neural Engine Processor chips on their SoC and in every iPhone, iPad, AppleTV+, etc., isn't feeding either Samsung or TSMC major investment backends. It's the AI backend servers and will be for the next decade.

I want to known when Apple is going to disclose their massive backend for EPYC/MI300 series for their expanded vertical cloud services, etc. They sure won't be using Nvidia or Intel as they cut ties with both years ago.
 
The real question is will Apple use chiplet or 3D fabric tech to change the entire chip design Apple Silicon chip? Otherwise, Apple will still stuck with limited chip design as Ultra chip is only as powerful as RTX 4060 or entry GPU.
4060? Maybe in some unoptimized tasks, but in what its designed for, it’s already beating 4090 at 1/4th the energy cost.
 
any advantage so far between iPhone 14 Pro and 15 pro in terms of CPU?. More battery life?, faster?, faster Siri?. Something that last generation was so slow at?. Even hdr5 or whatever can be done in iPhone 14, just Apple sells the idea that it was not possible fast enough. What would be the performance hit to run the same iOS features available in iPhone 15 but in a 14PM?. Just for very few games graphics are a little better.
Price hike justification.
 
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