Its good then that the 5nm and 7nm is just pure marketing that does not correspond to any actual structure size (keep in mind that Intel 10nm is higher transistor density than TSMC 7nm), also, the floor is closer to 2nm (with ångström precision on the fin structure) and that is for CPP, TSMC 7nm has a CPP of 40nm, their 5nm process maybe will get down to 35nm, so its a long long long way down to 2nm CPP.
You just spoke over the head of everyone on this thread except me and about 6 other people that understand semiconductor physics. You know that, right?
Most people hear 14nm, 10 nm, 7nm etc. and assume that all features have scaled and that there is a hard fast rule for defining geometries and how things fit together.
I know that Intel 10nm is equivalent or better than TSMC 7nm in density.
Going from 7nm to 5nm may mean active/switching power is lower but it may also mean that leakage is higher.
They are in risk/alpha production.
Mainstream by 2020? Maybe, depends on how dialing in the process works.
Until they run some real chips and some skew lots to see where the rubber really meets the roads, I'll wait.
They completed their DRM (Design Rule Manual), SPICE simulation and Process Design Kits (PDK).
I'm not taking anything away, but before I jump on the bandwagon I need to see real silicon and real yields.
I still remember TSMC 40nm to 28nm pain.