TSMC Paves Way for 5nm A14 Chip in 2020 iPhones

[Glideslope]

TSMC=Global Domination
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What would Apple do if Qualcomm buys TSMC.

That would cost apple arm and legs

Impossible

 

[eoblaed]

Remember the transistor is no longer mostly flat on the substrate and looks a lot like a skyscraper.
Fin-FET changed the game.

Also 7nm or 5nm defines smallest feature not every feature.

Thanks. I'm a software guy, not hardware, but I casually follow these types of things out of curiosity and general tech fandom. Just did some reading on FinFET ... seems like Moore's law continues to live, heh.

 

[cmaier]

But is it really? When people say 5nm they’re typically talking about the smallest feature. It doesn’t mean that the entire chip is at 5nm - a lot of items are significantly larger (like transistor gate pitch or interconnects).

Perhaps cmaier could chime in on this, but I imagine that even if 5nm was the smallest we could go that there’s still room for improvement by getting everything on the chip down to that size (if possible).

Pretty much nothing on the chip will actually be 5nm. Some distance between things may be 5nm. Anyway...

You can’t really improve things much by getting more of the stuff on the chip to those smaller sizes. The size of a transistor (by size we mean the ration of width to length of its gate) is determined by what it has to drive. If one transistor outputs to three receivers, you need to size it up enough to handle that load. Once you’ve size it up, then you need to size up whoever drives THAT, etc. Practically speaking, you can’t do much about it unless you go to radical new architectures that don’t execute the kinds of instruction sets we are talking about.

5nm is not as small as we can go, so we will just keep getting smaller. Other tricks will be used along the way, like improved semiconductors (SOI, strained semiconductors, maybe III-V semiconductors, etc.), better low-K dielectrics to reduce wire load, diagonal wiring layers, new and improved gate structures to provide better leakage characteristics, etc. etc.

 

[oneMadRssn]

TSMC isn't designing the chips. Think of them as a printer of Apple's design. They are just creating the 5nm process and spending the capital.

TSMC is designing the actual transistors, and designing the fabrication process.

In many ways, these are the most impressive and challenging steps in chip design.

 

[cmaier]

TSMC is designing the actual transistors, and designing the fabrication process.

In many ways, these are the most impressive and challenging steps in chop design.

And in other ways, they are not.

 

[Falhófnir]

It is considered the floor because it is pretty much impossible to make smaller transistors. Quantum computing will be next but that's still years away.

Not quite at 5nm, 3nm is *possible* but the reason 5nm is considered the floor is that the cost and complexity of 3nm starts to get pretty extreme, and yield rates are likely to drop off, so there's a big ? over whether it's financially viable to produce chips at that size (using pure silicon, I believe more exotic materials is mooted as the near term solution to overcome this, but no one seems to have a proof of concept worked out yet).

Its good then that the 5nm and 7nm is just pure marketing that does not correspond to any actual structure size (keep in mind that Intel 10nm is higher transistor density than TSMC 7nm), also, the floor is closer to 2nm (with ångström precision on the fin structure) and that is for CPP, TSMC 7nm has a CPP of 40nm, their 5nm process maybe will get down to 35nm, so its a long long long way down to 2nm CPP.

See above. The financials are why I say a lot of people consider it to be the floor, rather than it is actually the physical size limit beyond which it breaks the laws of physics to shrink further.

 

[cmaier]

Not quite at 5nm, 3nm is *possible* but the reason 5nm is considered the floor is that the cost and complexity of 3nm starts to get pretty extreme, and yield rates are likely to drop off, so there's a big ? over whether it's financially viable to produce chips at that size (using pure silicon, I believe more exotic materials is mooted as the near term solution to overcome this, but no one seems to have a proof of concept worked out yet).


See above. The financials are why I say a lot of people consider it to be the floor, rather than it is actually the physical size limit beyond which it breaks the laws of physics to shrink further.

I was designing chips when they said quarter micron was the practical floor. And 90nm. And etc. etc.

It’ll be fine.

 

[BvizioN]

so they can make the battery thinner

What's this obsession with sizes? As technology advances, size becomes meaningless. Just look back at how large electronic equipments were decades ago for not doing a small percentage of what they do now. So yes, stuff does get smaller and thinner if they don't need to be large and thick. Example? Look at the title of this article.

 

[Baymowe335]

TSMC is designing the actual transistors, and designing the fabrication process.

In many ways, these are the most impressive and challenging steps in chop design.

TSMC is a great company, but Apple is doing the architecture, which is the secret sauce. I'm not minimizing TSMC; I'm simply clarifying that they don't design the chips for Apple. Apple does and TSMC makes that design a reality.

 

[Falhófnir]

I was designing chips when they said quarter micron was the practical floor. And 90nm. And etc. etc.

It’ll be fine.

Well, they do always say where there's a will there's a way

 

[farewelwilliams]

What's this obsession with sizes? As technology advances, size becomes meaningless. Just look back at how large electronic equipments were decades ago for not doing a small percentage of what they do now. So yes, stuff does get smaller and thinner if they don't need to be large and thick. Example? Look at the title of this article.

My guess in the design process: since battery is one of the largest internal components in the phone, they target a particular battery life an average consumer needs (which dictates the size of the battery) and then design a product around that. Apple doesn't want to give the user too much battery life for several reasons. The big one is that the user might not develop a habit of charging nightly which may lead them to forgetting one day. Another is environmental. If the user doesn't make use of the battery before they upgrade their phone, Apple wasted materials on a huge scale.

I don't think Jony goes into the design studio and says "how can we make it thinner" (at least not for the iPhone these days). It's more like "what does the user need" and then proceeds to build a product with no excess materials wasted. For most of us on this forum, the needs are often not met, but for the average dumb 55 year old, it's enough.

 

[Jamers99]

Any bets on when we reach they reach 1nm? A20?

 

[BuddyTronic]

Are you sure? I'm seeing TMSC only valued at around the $30Bn range. Either way I don't think QC would buy them.

Doublecheck yourself. I can be wrong but not too often. Trust me more than yourself

 

[jhfenton]

Well, Qualcomm is a $70 Billion business, and you are asking what if they buy out and take over a $200 Billion business....

Are you sure? I'm seeing TMSC only valued at around the $30Bn range. Either way I don't think QC would buy them.

TSMC's total market cap is currently over $220B. Perhaps you are only looking at the ADR that trades on US markets? A majority of its market cap is traded in Taiwan.

 

[BuddyTronic]

Um... have you not heard of leveraged buyouts? Dell-EMC?

Yeah. Never heard of it.

Did you hear that Canada is gonna buy the USA? I didn’t - Leveraged Buyout.

 

[Kabeyun]

Crazy to ponder that they can make a microchip at conduit distances the same as X-ray wavelengths.

 

[darksithpro]

So what happens if TSMC and Intel can't shrink beyond 5nm?

 

[cube]

I thought 7nm was about the limit before quantum tunneling would see electrons jumping through the substrate. I guess they've come up with a practical solution to that and I equally guess I'm a bit behind the times on this, heh.

Intel would call this technology 7nm.

10nm Intel is like 7nm for the others.

 

[fourthtunz]

My guess in the design process: since battery is one of the largest internal components in the phone, they target a particular battery life an average consumer needs (which dictates the size of the battery) and then design a product around that. Apple doesn't want to give the user too much battery life for several reasons. The big one is that the user might not develop a habit of charging nightly which may lead them to forgetting one day. Another is environmental. If the user doesn't make use of the battery before they upgrade their phone, Apple wasted materials on a huge scale.

I don't think Jony goes into the design studio and says "how can we make it thinner" (at least not for the iPhone these days). It's more like "what does the user need" and then proceeds to build a product with no excess materials wasted. For most of us on this forum, the needs are often not met, but for the average dumb 55 year old, it's enough.

"For most of us on this forum, the needs are often not met, but for the average dumb 55 year old, it's enough.[/QUOTE]
I think its got more to do with pocket size and portability than age but for this average dumb 56 year old I'd really like for the IOS apps to take more advantage of the current processors(more multitasking) than shrink the size of the phone.

 

[cmaier]

So what happens if TSMC and Intel can't shrink beyond 5nm?

What happens if killer bunny bears attack Apple hq and steal all the mask designs?

Just as likely.

 

[BuddyTronic]

So what happens if TSMC and Intel can't shrink beyond 5nm?

Who knows. Probably there are other things to make the next ones better and better. Like a “hemi” or “direct injection”.

 

[BvizioN]

I don't think Jony goes into the design studio and says "how can we make it thinner" (at least not for the iPhone these days). It's more like "what does the user need" and then proceeds to build a product with no excess materials wasted. For most of us on this forum, the needs are often not met, but for the average dumb 55 year old, it's enough.

By the dump 55 years old, sure you man 99% of users who live outside MacRumors bubble, who think the rest of the world needs exactly what they need? Yeah, sure.
And no, I don't think Johny or anyone at Apple design stuff based on what customers ask for! Customers didn't ask for 3.5mm jack to be removed, customers didn't ask for all USB-c on MacBooks, customers didn't for camera bump, customers didn't ask for countless of things. And believe me, if Apple went by what customers wanted we would still be on a floppy disk area, DVD drives, or still have slide to unlock on iPhones, borning iOS skeuomorphism and countless of other stuff. Apple does not do that and it shouldn't so since is proven customers know ****.
Henry For once said, “If I had asked people what they wanted, they would have said faster horses.”

 

[AppleScruff1]

Who knows. Probably there are other things to make the next ones better and better. Like a “hemi” or “direct injection”.

Superchargers are good for big performance gains.

 

[mozumder]

Oh yay, a synthetic benchmark...

How can you compare it against real world applications? Oh wait, you can't, because they don't exist in iOS world.

I guess you didn't know Geekbench is based on real-world application.

 

[techwhiz]

Pretty much nothing on the chip will actually be 5nm. Some distance between things may be 5nm. Anyway...

You can’t really improve things much by getting more of the stuff on the chip to those smaller sizes. The size of a transistor (by size we mean the ration of width to length of its gate) is determined by what it has to drive. If one transistor outputs to three receivers, you need to size it up enough to handle that load. Once you’ve size it up, then you need to size up whoever drives THAT, etc. Practically speaking, you can’t do much about it unless you go to radical new architectures that don’t execute the kinds of instruction sets we are talking about.

5nm is not as small as we can go, so we will just keep getting smaller. Other tricks will be used along the way, like improved semiconductors (SOI, strained semiconductors, maybe III-V semiconductors, etc.), better low-K dielectrics to reduce wire load, diagonal wiring layers, new and improved gate structures to provide better leakage characteristics, etc. etc.

I knew I'd find you here.

Spot on about transistor and gate sizes.
I'd also like to add that the dominating factor is not transistor size it's wire and signal integrity.
Smaller wires have less current capacity and even if feature sizes shrink, the metal does not scale the same way.
For longer distances you may need fatter wires to reduce inductance and carry the current.
You may also need additional spacing due to signal issues. (aggressors)

When I'm doing development, I don't worry a lot about the gates. I now worry about the wires between those gates and flops. I look at the timing reports to see if I have heavily loaded nets that are going to be slow, or gates where the delay is much higher than expected.

Even if you make transistors faster, metal doesn't get faster in a shrink. Actually, metal might be slower. Yeah, I know the presumption is that with things closer in the shrink, we can ignore that metal is thinner/slower with lower current capacity.
I haven't see chips get smaller. I'm actually seeing more and more chips (not mobile) reach the reticle limit.

This isn't a free lunch. That's all I'm saying.
There are lots of challenges down in the single digits.
I'd like to see the performance of process monitors (ProcMon) and ring oscillators. Some skew lots with sample structures would be nice too.
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I was designing chips when they said quarter micron was the practical floor. And 90nm. And etc. etc.

It’ll be fine.

I was there too; .6, .35 and .25 micron.
I remember them saying we would hit a brick wall a .1 micron.
I remember them saying 90nm, then 48nm and on and on.....

I've seen optical processes using the capillary properties of water along with the refraction properties to give better performance on the lenses to focus in the lithography. We now have EUV being developed for 2020 and beyond.

There are barriers and we keep jumping over them in different ways.

I guess I'm really showing how long I've been around this stuff and how much of a true geek I really am.