TSMC Ramps Up Production of 7nm Chips Ahead of 2018 iPhones, Invests $25 Billion to Move to 5nm by 2020

[PickUrPoison]

A quick google search is all that it takes. Anyway
https://www.gsmarena.com/samsung_patent_shows_selfie_camera_may_be_behind_the_screen-news-29217.php
https://mobilesyrup.com/2018/03/09/apple-patent-display-hidden-camera/

A quick google search may not be as useful as you think. Just because Apple is working on a technology and has a few (or dozens of) patents doesn’t mean the technology is of sufficient quality to be useful or is manufacturable yet.

It may require another ten years of development to be viable to use in a product. The Apple patent is a continuation of patents from 2011, 2015 and 2017, which themselves are likely based on many years of effort as well.

 

[EdT]

What are the implications of this?

7nm refers to the size of a single transistor that makes up the CPU on a chip. The smaller you can make a transistor the more of them you can put into the same physical space, and the more transistors the more powerful the CPU. There are several design challenges to shrinking the size of a transistor however. The physical properties of a transistor are based upon the shape and the intentionally added impurities to the silicon to create the electrical properties that make it a transistor. Get the shape the transistor is supposed to be a little wrong or the impurities in the wrong proportion and the CPU wafer is either sub-par as far as performance goes or perhaps even non-functional. The smaller you make the transistor the more difficult it is to keep everything within size and material tolerance.

Bigger CPU chips use more power, and by making the transistors smaller you can fit a lot more of them into the same space, making the CPU both smaller and more powerful. There are trade offs because of heat tolerance and even quantum limitations but that's the 30 second explanation.

A slightly longer but more detailed but still easy to understand explanation here:
processors-process-size

 

[cmaier]

This is just a guess, but the GPU has previously been outsourced. I believe it's expected for the A12 to be Apple designed. By doing this they can design it around being on the CPU die itself.

It’s already on the die and designed by Apple. They buy the architecture, however. In the future they are doing the architecture/front end design themselves.

 

[DaveWil]

7nm refers to the size of a single transistor that makes up the CPU on a chip. The smaller you can make a transistor the more of them you can put into the same physical space, and the more transistors the more powerful the CPU. There are several design challenges to shrinking the size of a transistor however. The physical properties of a transistor are based upon the shape and the intentionally added impurities to the silicon to create the electrical properties that make it a transistor. Get the shape the transistor is supposed to be a little wrong or the impurities in the wrong proportion and the CPU wafer is either sub-par as far as performance goes or perhaps even non-functional. The smaller you make the transistor the more difficult it is to keep everything within size and material tolerance.

Bigger CPU chips use more power, and by making the transistors smaller you can fit a lot more of them into the same space, making the CPU both smaller and more powerful. There are trade offs because of heat tolerance and even quantum limitations but that's the 30 second explanation.

A slightly longer but more detailed but still easy to understand explanation here:
processors-process-size

Also electricity travels at about 1 foot per nanoseconds, so the shorter the distance the faster the computer.

 

[goobot]

A quick google search may not be as useful as you think. Just because Apple is working on a technology and has a few (or dozens of) patents doesn’t mean the technology is of sufficient quality to be useful or is manufacturable yet.

It may require another ten years of development to be viable to use in a product. The Apple patent is a continuation of patents from 2011, 2015 and 2017, which themselves are likely based on many years of effort as well.

Ok? Besides the fact that you were acting like it was entirely impossible but your reasoning was that light can’t go through the screen. We have seen phones with finger print scanners that already do this with oled screens so obviously it is already currently possible. I highly doubt this tech is far out there because there are plenty of companies other than Samsung and Apple working on it. Again a quick google search would probably show you all of them.


Edit: didn’t realize it was a different poster.

 

[curmudgeonette]

One reason for the delay is that they can't integrate the GPU on the 10nm CPU - anybody knows the details, do enlighten us here.

Intel is trying to have a GPU on the 10nm CannonLake chips. Rumor has it that the standard configuration is 40 EUs. In comparison, the standard Kaby Lake GPU is 24 EUs. A 24 EU GPU takes up about the same space as four CPU cores. Thus, in a dual core 40 EU chip, the GPU might be three quarters of the die. If there's one single silicon defect, odds are that it is in the GPU portion. Consequently, Intel is having a yield problem. They are salvaging defective chips by disabling the GPU and selling, er giving away, GPUless chips.

 

[GuruZac]

I would much rather have a TSMC sourced chip than Samsung. I feel Apple probably has better control over the TSMC process than Samsung, though that could be entirely off base. I've still got my trusty iPhone 7 Plus and have zero complaints with the A10's performance or the phone's battery life. Still great. I think beginning with the A9, these chips have surpassed the ability of the phone's functionality. I was using a friend's 6S Plus, and it still feels basically the same as my 7 Plus, and played around with my buddy's X, and it doesn't feel any different. I understand the massive jump in performance to facilitate AR, etc, but the A11 and beyond seem way over kill unless Apple intends to use the A series chipset as a basis for the desktop chips moving forward.

 

[UltimaKilo]

Intel’s sizes are not directly comparable with TSMC or Samsung’s. I’d say their 10 is about equivalent to the 7 everyone in mobile is at. Everyone is having problems at this size because the chips are tiny.

This.

5nm? slightly faster (though probably not noticeable in most tasks) with slightly more energy efficiency (though probably packaged with less battery to deliver "the same great battery life" in the name of "thinner").

And one step closer to the theoretical minimum, at which point this game of a smaller nm number can no longer be played and CPU spin will have to become about something else. The literature on the topic implies 4nm or maybe 3nm is the cap, with bias toward 4nm.

One supplier?

• Hype of parts shortages at launch to feed the annual frenzy of trying to be "first"... and then just trying to get one as if they will remain scarce for 6 months (but not really 6- that's just implied, as everyone who wants one should be able to give Apple money before Santa comes down the chimney).
• A variety of "all eggs in one basket" scenarios.

3.5nm is already underway, even though it's maybe 7-8 years away, there is already successful experimentation at that size.

Apple will be crippling any A12 gains by giving the iPhone the least amount of system RAM of all rival flagship Android smartphones. iPhone 3GB to many other smartphones sporting 6GB to 8GB of RAM. That's totally messed up on Apple's part. Almost no one will see the A12's edge over Qualcomm and Samsung processors in everyday use. Nowadays, social apps are being valued much higher than any hardware Apple can ever hope to offer. Qualcomm will never give in to Apple in terms of processor power, so it will be a very costly war costing Apple huge amounts of money for marginal gains.

Why the heck do you need more than 4GB of RAM on a phone? You living in 2025?

I would much rather have a TSMC sourced chip than Samsung. I feel Apple probably has better control over the TSMC process than Samsung, though that could be entirely off base. I've still got my trusty iPhone 7 Plus and have zero complaints with the A10's performance or the phone's battery life. Still great. I think beginning with the A9, these chips have surpassed the ability of the phone's functionality. I was using a friend's 6S Plus, and it still feels basically the same as my 7 Plus, and played around with my buddy's X, and it doesn't feel any different. I understand the massive jump in performance to facilitate AR, etc, but the A11 and beyond seem way over kill unless Apple intends to use the A series chipset as a basis for the desktop chips moving forward.

The iPhone 6S was a huge leap over the 6, yes, but you can definitely see the difference between the A9 and A11. I will agree that the difference between the 7 and X as far as performance is almost unnoticeable since the A10 already has plenty of headroom.

 

[lec0rsaire]

This.



3.5nm is already underway, even though it's maybe 7-8 years away, there is already successful experimentation at that size.



Why the heck do you need more than 4GB of RAM on a phone? You living in 2025?



The iPhone 6S was a huge leap over the 6, yes, but you can definitely see the difference between the A9 and A11. I will agree that the difference between the 7 and X as far as performance is almost unnoticeable since the A10 already has plenty of headroom.

The difference between the 7 Plus and 8 Plus/X is not huge but it is instantly noticeable as soon as you use it. Since the 7s already perform great with iOS 11 the real world difference is insignificant but it is there. The UI and camera just feel snappier. I can only imagine how awesome the A12 will be. I hope they pair it with 4GB RAM across the board.

 

[Baymowe335]

They are doing 3nm is 2021.

 

[Precursor]

5nm? slightly faster (though probably not noticeable in most tasks) with slightly more energy efficiency (though probably packaged with less battery to deliver "the same great battery life" in the name of "thinner").

Actually 5nm chip architecture half the size of 7nm, so the difference would a noticeable as 7nm to 10nm, or 10nm to 14nm (which are all half the size of the former)

 

[Tech198]

Actually 5nm chip architecture half the size of 7nm, so the difference would a noticeable as 7nm to 10nm, or 10nm to 14nm (which are all half the size of the former)

Smaller package + more room for components if needed. externally to the chip. With these advancements, your iPhone would soon tell you when you cough as well (jeez)

 

[cmaier]

Also electricity travels at about 1 foot per nanoseconds, so the shorter the distance the faster the computer.

We usually think of at 6pS/mm, but in any case that’s not much of a factor. At the scales in a microprocessor, time of flight is an issue only for a small percentage of the wires. What dominates is the time it takes to make a transition. In other words. Each wire has an effective capacitance, and you put a ramp on one side and need to see the ramp on the other. The time delay between the ramps is the time of flight. But even at the input, the ramp is not instantaneous. The transitor drain wants to charge the capacitor but can’t do so instantaneously. We usually worry about the time it takes to get from 20 percent of Vdd to 80 percent.

Smaller geometries can actually HURT this, because we decrease the space between the wires without making a proportional decrease in the height of the wires. Capacitance is proportional to the cross sectional area between the wires (which decreases when we shrink the height of the wires) divided by the distance between the wires. By shrinking the length of the wires we also decrease the capacitance because that decreases the cross sectional area. (I am ignoring resistance to make this simple). The net effect is that interconnect capacitance scales worse than the transistor size in the real world. Because of this we can’t scale transistor width at the same rate we are scaling transistor length. You need more width to length to increase the drive strength. But since there is a transistor at the far end of your wire, this adds more capacitance (a transistor source looks like a mos capacitor). Which means you need to beef up the driver a tad more. And the cycle repeats until you find the ideal transistor size.

If you make your wires very thin, you increase resistance, which has the effect of allowing the ramp to increase faster at the source end, but then you get time of flight being more of a problem. You also increase the risk of parasitic cross coupling, which is incredibly hard to model and predict (and makes it very hard to bin parts). One way to deal with that is to use special wiring schemes like differential wiring, one 1 of N wiring. The latter was intrinsity’s specialty, which may mean Apple is doing it, but it has its own trade offs.

In any event, this is why transistor sizes do not actually shrink anywhere near as fast as the fab node sizes. There are probably zero transistors in a 7nm design that have channels that are 7nm wide and 7nm long. Also probably very few wires that are actually 7nm wide or 7nm spaced.

 

[DaveWil]

We usually think of at 6pS/mm, but in any case that’s not much of a factor. At the scales in a microprocessor, time of flight is an issue only for a small percentage of the wires. What dominates is the time it takes to make a transition. In other words. Each wire has an effective capacitance, and you put a ramp on one side and need to see the ramp on the other. The time delay between the ramps is the time of flight. But even at the input, the ramp is not instantaneous. The transitor drain wants to charge the capacitor but can’t do so instantaneously. We usually worry about the time it takes to get from 20 percent of Vdd to 80 percent.

Smaller geometries can actually HURT this, because we decrease the space between the wires without making a proportional decrease in the height of the wires. Capacitance is proportional to the cross sectional area between the wires (which decreases when we shrink the height of the wires) divided by the distance between the wires. By shrinking the length of the wires we also decrease the capacitance because that decreases the cross sectional area. (I am ignoring resistance to make this simple). The net effect is that interconnect capacitance scales worse than the transistor size in the real world. Because of this we can’t scale transistor width at the same rate we are scaling transistor length. You need more width to length to increase the drive strength. But since there is a transistor at the far end of your wire, this adds more capacitance (a transistor source looks like a mos capacitor). Which means you need to beef up the driver a tad more. And the cycle repeats until you find the ideal transistor size.

If you make your wires very thin, you increase resistance, which has the effect of allowing the ramp to increase faster at the source end, but then you get time of flight being more of a problem. You also increase the risk of parasitic cross coupling, which is incredibly hard to model and predict (and makes it very hard to bin parts). One way to deal with that is to use special wiring schemes like differential wiring, one 1 of N wiring. The latter was intrinsity’s specialty, which may mean Apple is doing it, but it has its own trade offs.

In any event, this is why transistor sizes do not actually shrink anywhere near as fast as the fab node sizes. There are probably zero transistors in a 7nm design that have channels that are 7nm wide and 7nm long. Also probably very few wires that are actually 7nm wide or 7nm spaced.

Interesting, thanks.