Thunderbolt 1.0 is receiving a 16Gbps x4 2.0 pci-e stream using 4 TX/RX pairs (lanes), applying some signal processing and re-transmitting using 2 TX/RX pairs along the Thunderbolt channel. We can conclude this based on the TB pinout
http://en.wikipedia.org/wiki/Thunderbolt_(interface)
Thunderbolt 1.0 has 2x10Gbps channels, 10Gbps dedicated for pcie and 10Gbps for displayport. No way of aggregating them.
Thunderbolt 2 achieves it's 20Gbps with aggregation. Same link tells us "At the logical level, Thunderbolt 2 enables channel aggregation, whereby the two previously separate 10 Gbit/s channels can be combined into a single logical 20 Gbit/s channel."
I'm guessing The TB 2.0 controller will uprate the pci-e electrical link to x4 3.0 to be able to transmit the full 20Gbps. Then manufacturers just drop in the TB 2.0 chip in their existing designs and can claim 20Gbps with pci-e 3.0 cards or 16Gbps with pci-e 2.0 cards. A cheap solution to doubling bandwidth and getting upgrade $$.