ZildjianKX said:
I don't think wanting a 3 GHz G5 is asking too much... I personally think they should be aiming for higher than 3 GHz for one year... just my $0.02.
Because, you know, Intel jumped a whole gigahertz last year.
oingoboingo said:
You never know...maybe 2.6GHz will replace the entry level 1.6GHz, and we'll have 3GHz systems 'paper launched' at WWDC, with actual availability in September, just like the original G5 launch.
I could be dead wrong, but let's put it this way... I think Apple is being tight, tight, tight about anything they release right now. Remember that warning to the Seed program last week? If they don't even want programmers talking about what's in the OS update, what do you think they would do to anyone who leaked that there were machines over 2.0ghz?
Also... Would Steve let there even be a remote possibility that the 3.0s would be preannounced? This is, at best, an appetite whetter. It's to get attention from people like us that slaver over the rumors.
In fairness to Apple, I don't think Apple itself has spent 12 months preparing for Rev. B...more like they've waited this long for IBM to solidify their supplies of faster PPC970 and PPC970FX chips...which is what the article was about.
Exactly.
3GHz or not, a 600MHz increase over the previous top-end (or put it another way, a 30% jump) is quite a welcome improvement, and will push the G5s back into serious competition with newer Opteron, Athlon 64 and Pentium 4 systems.
It's more than 200mhz and dropping the line, that's for sure.
LaMerVipere said:
WTF? No 3GHz within a year like steve promised? AAAAAAH!!! THIS IS ANARCHY! Not to mention bad business, like, oh "100 million songs within a year and 30 million of that will come from the iTunes/Pepsi giveaway!" NOT. "3GHz within a year!" NOT. C'mon apple, get with the program already.
Psssst... It hasn't been a year yet.
macridah said:
Here is the only way I see steve making good on his promise to deliver a 3 ghz power mac. Here is the lineup:
dual 2.2 ghz
dual 2.6 ghz
single 3.0 ghz
There will also be a slash in cinema displays. I have spoken ...
Except that a dual 2.6 would slaughter a single 3.0. The standard gain from SMP-aware applications is around 50%, so those dual 2.6s will be more like single 3.9ghz machines.
LaMerVipere said:
Well we are only holding Steve to his word. He could eliminate such criticism if he was more careful with his wording. To make statements, as he did, about hitting 3GHz within a year, and then, presumably, failing to do so, isn't any fault of ours. How can u hold it against people for comparing what steve said and the apparent reality of the situation? Damn that reality distortion field. *shakes fist as sky*
Wrong, bucko. You're shouting before the deadline is even past. Steve hasn't failed until the end of the Keynote at WWDC, and even then, the wording makes it possible that he could claim that "summer" means August.
How about you actually do what you say you're doing and wait for the "apparent reality of the situation," hmmmm?
Basicly, IBM will have no trouble making a dual core chip, but I doubt the chips they will be supplying Apple will be dual cores, but whatever chip they derive from POWER 5 I would think will probably have the SMT capability (works a lot like Intel's Hyper-Threading but better). Also, POWER 5 has an on-die memory controller and I beleive uses a full implementation of hyper-transport for the FSB, so anything AMD may have on us now is just something that IBM's playing with right now or have been doing for a while already.
Read about it here.
Single-chip Power5s present as four cores (two logical, two virtual, according to the article), with 120 registers for integer and FP, 8 execution units, and a shared 1.92MB L2 cache (3 640k caches on independent buses). The chips operate and a 128bit-128bit dual single-directional bus (functionally a 256-bit 2Ghz FSB) with a half-clock interconnect to other MCMs (1ghz 128-bit), and an on-chip DDR memory controller with a 6GB/s I/O bus. The 32MB L3 cache and memory bus are separated, allowing for a theoretical memory bandwidth of 20GB/s, with the L3 on a 1GHz on-die bus.
From the article:
In any case, a typical 64-way SMP POWER5 system composed out of 32 chips will support 1TB RAM at start.
..
Well, if you just repeat the system density of p655, and have two of such systems in every 4 U of rack height, there comes a 2 TFLOPs cluster with 2 TB RAM with a peak memory bandwidth of more than 2 TB / second, all in one rack, with a bit of room to spare! Just remember a proper fast interconnect with distributed shared-memory capability...
I think there would be no problem at all making the 975 a dual-core chip with a memory controller on-die. In other words... VROOOOM!