RISC doesn’t require that at all. It’s all done by compilers, and so the main difference is whether you think a CPU is capable of doing better optimizations at run time than the compiler can do at compile time.Your right, should have conveyed it differently. The term natively was the wrong word to utilize. I was trying to show the difference between RISC instruction set requires one to write more efficient software with fewer instructions, versus CISC which is using complex instructions.
In the end it’s been proven repeatedly that all else being equal, you can get identical performance from RISC and CISC and burn 20% less power in RISC, or you can get 20% more performance from RISC as compared to CISC at the same power budget. The structures are essentially identical, except for the addition of a much more complicated instruction decoder (with a micro-op sequencer, microcode ROMs, etc.) in CISC.