Looking forward to seeing the first Macs with M3 chips!!
Got a tip for us?
Let us know
Become a MacRumors Supporter for $50/year with no ads, ability to filter front page stories, and private forums.
Apple Orders Entire Supply of TSMC's 3nm Chips for iPhone 15 Pro and M3 Macs
- Thread starter MacRumors
- Start date
- Sort by reaction score
Just look at what they're doing with their upgrade prices.
Memory and SS storage are at very cheap prices historically.
Their upgrade prices are ridiculously higher than ever.
Currency changes in other countries.
For sure they had to adjust but I guarantee they will make sure they make more than just adjusting to maintain their profit margins.
iPad base prices steadily creeping.
Add the touch bar. Increase prices by $200/300 Remove the touchbar and add mini led. Increase the prices.
They're pretty slick about it and luckily for them their users don't seem to notice much.
This is why I skipped the iPhone 14 and will be going for the iPhone 15. The 4nM chip was just too bulky for me
Impressive that Apple can use up all of TSMC’s 3nm capacity. That will really help them stay ahead of the competition.
It's a "technology that TSMC claims is like 3nm would be" if we followed the old antiquated cycle.
In December 2022, at IEDM 2022 conference, TSMC disclosed a few details about their 3nm process technologies: contacted gate pitch of N3 is 45 nm, minimum metal pitch of N3E is 23 nm, and SRAM cell area is 0.0199 μm² for N3 and 0.021 μm² for N3E (same as in N5).
3 nm process - Wikipedia
My understanding is that N3B should be considered a completely different node(or node family, which happens to be a dead end) that is unrelated to N3E/N3P/N3X/N3S since they are so different. The designs on N3B will have to be majorly reworked and there is no easy conversion without major redesign, and FinFlex makes that even more complicated. This is almost like starting from scratch as after the redesign for the new node they need to start the validation and verification all over again which includes tap in, mask production, and tap out to even start testing. Then it is likely that they will need to repeat that process with multiple respins to get it functional or functional with the target performance. This is the major fixed cost that needs to be amortized over the entire chip run. This is unlike a N3E design that can easily be ported to the subsequent nodes in the family(N3P N3X etc) where the designs should just be compatible and work, which is one of its advantages.
I have no inside info so I do not know yields or how many chips apple is projected to need for things to make economic sense and have a contiguous product roadmap that matches with consumers target life cycles. And I may be wrong but I kind of hope that Apple reserves the N3B run for the A17 bionic and any other custom chips(or chiplets), and can hold off on the M3 for a N3E node, then the logic for the various cores can be used on the M3pro(max ultra or whatever) with N3P node to have an improving product line. And yes I do realize the A17's performance and efficiency cores will likely be the same as the M3 family so this may just be a moot point. However that could also mean that apple may be effectively locked in to making the entire M3 line on the N3B node for economic reasons while competitors use N3E and other future nodes to have higher performing products. Just some random thoughts.
Good info, thanks! But as for being locked in... no way. With all the essential design done, even if they have to lay out the whole thing again and make a few changes, they've got enough volume from Macs (and iPad Pros) to redo their chips on N3E.
Would love to visit a TSMC fab one day. ASML EUV equipment would be crazy to see.
This report (and the news reporting surrounding it) seems to suggest that such a brain drain occurred. Like you said, it could be wrong though. I'm wondering if @Confused-User can confirm anything about this.
At Apple, a War for Chip Talent Intensifies
For more than a decade, Apple’s silicon engineering group has helped give Apple a competitive edge in smartphones and laptops. The custom chips it designsmake its products snappier to use or help them eke out an hour or more of extra battery life. Last year, though, Apple’s chip department hit a ...
www.theinformation.com
Very interesting.It's a "technology that TSMC claims is like 3nm would be" if we followed the old antiquated cycle.
In December 2022, at IEDM 2022 conference, TSMC disclosed a few details about their 3nm process technologies: contacted gate pitch of N3 is 45 nm, minimum metal pitch of N3E is 23 nm, and SRAM cell area is 0.0199 μm² for N3 and 0.021 μm² for N3E (same as in N5).
3 nm process - Wikipedia
en.wikipedia.org
So its more of a marketing tool than a true mathematical calculation of size.
I guess using it in the way the marketing was intended dropping from the 5nm to a 3nm in terms of marketing design will be a more substantial increase in performance and efficiency compared to what the M2 is to the M1.
Sorry, I have no definitive knowledge. However, none of the people at Apple that I know think that this has happened. None of them have definitive knowledge either, but they do know their teams. So... I'm skeptical there's a problem. I can't disprove it though.This report (and the news reporting surrounding it) seems to suggest that such a brain drain occurred. Like you said, it could be wrong though. I'm wondering if @Confused-User can confirm anything about this.
At Apple, a War for Chip Talent Intensifies
For more than a decade, Apple’s silicon engineering group has helped give Apple a competitive edge in smartphones and laptops. The custom chips it designsmake its products snappier to use or help them eke out an hour or more of extra battery life. Last year, though, Apple’s chip department hit a ...
Edit: Let me be clear, people leave all the time. Even some of the rock stars. But others join. That's normal. I'm talking about an unusual level of churn, as described in those news reports you mentioned.
Intel CEO Pat Gelsinger is nonplussed:
www.tomshardware.com
Intel's CEO Fires Back at 3nm Delay Rumors
Arrow Lake, Granite Rapids, and Sierra Forest scheduled to arrive in 2024.
Apple is not operating like that. Even with the increasing profit from the services division, there’s no indication that Apple would subsidize their hardware. Unlike other companies that use subsidy to increase volume, Apple is using its brand value to attract buyers while keeping high margins.
Next, I shall tell Tim Cook off for not solving world hunger and increasing the cost of groceries!
They've always subsidized new hardware by keeping prices stable. Apple even subsidized their own commercials. Spending way more than justifiable on iPod commercials to create a halo effect for the Mac. Basically every company is subsidizing their products when they make an investment. Only when the customer pays a vague kickstarter project upfront, then there was no corporate subsidy involved. You'll never know how much of a product you'll end up selling. So when you calculate in the development costs per unit, you can only make an educated guess. Which means you basically give the first units away for free, hoping to make a break even later on. What's that if not a hidden subsidy?
Basic aspects of the Apple Silicon ecosystem spanning from the Apple Watch with S7 to the Mac Studio with M1 Ultra will never be matched by any company. So their lead is infinite, until something better than ARM chips comes along. Apple leads this silicon era just as Intel ruled x86.
50 dies/chips per wafer is up in the M1/M2 Max sized die. Apple wouldn't be doing entire runs of just those. Some breakdowns for various die sizes that Apple has used which could be used on TSMC N3 ( it didn't take any 'shrink' gains of N3 to get some more reasonable sized dies).
( used die yield calculator here : https://isine.com/resources/die-yield-calculator/ (used default density of 0.2 and an alternative 0.05 here. something higher than 0.2 would just consume more wafers. ).
| Die Size ( mm^2) | H (mm) | W (mm) | Total dies(package) / 300mm | Good Dies (d 0.2) | Yield | GD (0.05) | Yield | |
| M1 Max (estimated) | ~448 | 22.46 | 19.96 | 115 | 50 | 43.5% | 93 | 80.9% |
| M2 Max Latop (estimated) | ~463 | 22.66 | 20.46 | 110 | 47 | 42.7% | 89 | 80.9% |
| Mn Ulrra ( estimated) | aggregate to 2 * M1 Max area | 22.46 | 19.96 | 25 | ||||
| Mn Extreme (rough est.) | aggregate to 4 * M1 Max area | 22.46 | 19.96 | 12.5 | ||||
| M1 Pro | 246 | 12.98 | 18.95 | 224 | 140 | 62.5% | 198 | 88.4% |
| M2 Pro (est) | 262 | 13.98 | 19.95 | 195 | 115 | 59.0% | 170 | 87.2% |
| M1 | 153 | 10.99 | 10.96 | 479 | 378 | 78.9% | 451 | 94.2% |
| M2 (partial est) | 155 | 12.55 | 12.35 | 367 | 271 | 73.8% | 340 | 92.6% |
| A15 | 108 | 12.55 | 8.58 | 538 | 436 | 81.0% | 512 | 95.2% |
| A16 |
Oddly didn't easily find a die size estimate for A16. it is bigger than the A15 die. I highly doubt though that Apple would want ot push the die size bigger than the A15 if had TSMC N3 avaialble. Typically plain Axx have been in the 85-95mm^2 range.
IHMO, the Ultra and Extreme won't be literally the "Mx Max" that is used in the laptop anymore. But to estimate the area those various chiplets will add up to using a 'sliced up' Max area size. ( The picking the 0.2 defect usable dies for M1 Max . chiplets should push yield up a bit, but complex packaging may be a trade off. ). so for Ultra/Extreme that is number of die collections that go into a package after pull multple dies from wafer(s).
For something relatively small to the M-series like the A15 Apple should be able to get 400-500 dies per wafer. In contrast something like the Extreme would 'eat' wafers at an order of magnitude faster pace.
45K completed wafers per month is a furious pace that neither the 'bleed edge only' iPhone ( ~ 100M/yr ) or Mac ( 20-30M/ yr ) could sustain for a whole year. Makes the TSMC N3E super near term talk a bit dubious. The timing is wrong for the iPhones. It wouldn't be surprsing to see the AR/VR headset SoC(s) thrown in also.
To get perspectives on volumes and wafer consumption taking the defect 0.2 rate good dies per wafer and looking at a range of run rates.
| Dies(packages)/Waf (defects 0.2) | Waf per 20K dies | Waf/100K dies | Waf/1M dies | Waf/10M dies | |
| Mn Extreme (rough est) | 12 | 1,667 | 8,333 | 83,333 | 833,333 |
| Mn Ulra ( rough est ) | 25 | 800 | 4,000 | 40,000 | 400,000 |
| M2 Max | 47 | 426 | 2,128 | 21,277 | 212,766 |
| M1 Pro | 140 | 143 | 714 | 7,143 | 71,429 |
| M2 | 367 | 54 | 272 | 2,725 | 27,248 |
| M1 | 378 | 53 | 265 | 2,646 | 26,455 |
| M2 Pro | 115 | 174 | 870 | 8,696 | 86,957 |
| A15 | 436 | 46 | 229 | 2,294 | 22,936 |
so 10M A15 generates about the same ballpark wafer consumption at 1M M2 max would ( 22,936 vs 21,277 ). Similarly 20K extremes about the same ballpak consumption as 100K M2 Max . 1M M2 sized dies as 100K M2 Max.
45K/mo would get about 20M A15 sizesd does finished in a month ( 3 month ramp to get to ~60M). 1.5-2M Ultra could eat up about two months though.(but the Studio isn't that old so 'millions' super fast probably isn't an option. Mac Pro certainly isn't going to do those kinds of numbers. ) 20M M2-sized dies really isn't that much at 45K/mo run rates. If just wait until after the initial A17 demand bubble build they can weave those in spread out over several months. [ It is Digitimes though so 45k may be some wonky number. At 25K/mo still wouldn't need to split much if did larger M-series modules in the iPhone "off season" before the May-July pre-release demand bubble. A 45K/mo rate out of N3E with fewer steps would be more believable. ]
20K Extremes with less than 2,000 wafers could have been done early in N3 ramp. I suspect Apple's plan was to finish off end of 2022 with a new Mac Pro that they could squeeze into the early N3 build up (which on 2018-2019 'plan' would happed earily in Q4 than it did.). Similar with the AR/VR headset. Again relatively low numbers means don't need 20K wafers/mo to get the product out the door.
Splitting these M3 family onto something separate than A17 doesn't really make much sense if Apple had both N3 designs mostly done. N3E starts too late to do much for iPhone. [ Maybe if the iPhone Max/Ultra is the only one that gets the new chip can cut the volume need to stockpile at launch way down. ]
85M is probably high for the total iPhone sales.
One estimate.
IDC, Morgan Stanley Q4 iPhone sales estimates revealed – Apple Must
www.applemust.com
the top end iPhone 14 variants are 65-80% of iPhone sales. The other models do sell in substantive volume (relative to units sales of all other cell phones) . If Apple keeps the "last years Max SoC " for the next round only really need to cover the Max (and if Apple tossed in a Ultra model on top). If there is a huge performance gap That will be more than 50% of iPhone 15 sales, but it will still have healthy competition with the more affordable A16 powered unit.
The A17 on N3-family should likely bring a smaller die than the A15/A16 if Apple uses FinFlex effectively. Wafer costs going up will also put lots of incentive for them to boost the number of good dies per wafer also.
When it comes to what N3 will bring there are a few things to remember.
#1: Nobody knows Apple wafer costs. (Actually, there is no "price list" for the nodes we’re discussing, individual contracts/conditions are negotiated and agreed upon. Apple has been a financial corner stone for TSMC when it comes to building new node capacity. Their deals are unlikely to match anyone elses.)
#2: the listed improvements in speed or power draw are per gate. So if you use your increased logic density to advance the architecture, if that increases the gate count so will the power draw. (Very loosely as you are unlikely to run all parts of the SoC at full blast. The message rather is that power scales with the gates - you can’t increase the number of logic gates by 70% at the same frequency and expect power to remain constant.)
#3: increased density vs. 5nm refers only to logic. SRAM and I/O remain unchanged.
So while the new node will bring improvements, these will need to be balanced and in all likelyhood limited along any given axis. For instance, you may see the increased logic density be partially utilized to reduce chip area, increasing SoC yield/wafer and thus contain production costs. It is also likely to be utilized to implement architectural enhancements where they bring more benefit/W than increasing clocks. The whole will be constrained to roughly the same overall power draw, but improvements to power management could increase average total runtime/unit energy.
Example: 30% more logic gates, 15% overall area reduction and a tiny increase in maximum clock frequencies, say 5%. This would bring a small overall gain in performance, a larger improvement where the architectural improvements come into play, at a modest increase in overall production cost, and still fitting within all existing power constraints. Or some variation of this. The days where a process node change could drive a large shift in performance are gone.
guess you never heard of a balance sheet or profit and loss statement or cash flow. Apple absorbs costs all the time. If they never release a car, they absorbed possibly 100s of millions of dollars, perhaps billions of dollars on a long shot.
they absorb costs of developing software that they provide for free. they absorb costs of upgrading their free software products. just because they absorb costs on something doesn't mean they don't have good motivations or reasons for doing so.
just wanted to say thanks for caring so much and posting all your desktop research to share it with others.50 dies/chips per wafer is up in the M1/M2 Max sized die. Apple wouldn't be doing entire runs of just those. Some breakdowns for various die sizes that Apple has used which could be used on TSMC N3 ( it didn't take any 'shrink' gains of N3 to get some more reasonable sized dies).
( used die yield calculator here : https://isine.com/resources/die-yield-calculator/ (used default density of 0.2 and an alternative 0.05 here. something higher than 0.2 would just consume more wafers. ).
Die Size ( mm^2) H (mm) W (mm) Total dies(package) / 300mm Good Dies (d 0.2) Yield GD (0.05) Yield M1 Max (estimated) ~448 M2 Max Latop (estimated) ~463 Mn Ulrra ( estimated) aggregate to 2 * M1 Max area Mn Extreme (rough est.) aggregate to 4 * M1 Max area M1 Pro M2 Pro (est) M1 M2 (partial est) A15 A16
Oddly didn't easily find a die size estimate for A16. it is bigger than the A15 die. I highly doubt though that Apple would want ot push the die size bigger than the A15 if had TSMC N3 avaialble. Typically plain Axx have been in the 85-95mm^2 range.
IHMO, the Ultra and Extreme won't be literally the "Mx Max" that is used in the laptop anymore. But to estimate the area those various chiplets will add up to using a 'sliced up' Max area size. ( The picking the 0.2 defect usable dies for M1 Max . chiplets should push yield up a bit, but complex packaging may be a trade off. ). so for Ultra/Extreme that is number of die collections that go into a package after pull multple dies from wafer(s).
For something relatively small to the M-series like the A15 Apple should be able to get 400-500 dies per wafer. In contrast something like the Extreme would 'eat' wafers at an order of magnitude faster pace.
45K completed wafers per month is a furious pace that neither the 'bleed edge only' iPhone ( ~ 100M/yr ) or Mac ( 20-30M/ yr ) could sustain for a whole year. Makes the TSMC N3E super near term talk a bit dubious. The timing is wrong for the iPhones. It wouldn't be surprsing to see the AR/VR headset SoC(s) thrown in also.
To get perspectives on volumes and wafer consumption taking the defect 0.2 rate good dies per wafer and looking at a range of run rates.
Dies(packages)/Waf (defects 0.2) Waf per 20K dies Waf/100K dies Waf/1M dies Waf/10M dies Mn Extreme (rough est) Mn Ulra ( rough est ) M2 Max M1 Pro M2 M1 M2 Pro A15
so 10M A15 generates about the same ballpark wafer consumption at 1M M2 max would ( 22,936 vs 21,277 ). Similarly 20K extremes about the same ballpak consumption as 100K M2 Max . 1M M2 sized dies as 100K M2 Max.
45K/mo would get about 20M A15 sizesd does finished in a month ( 3 month ramp to get to ~60M). 1.5-2M Ultra could eat up about two months though.(but the Studio isn't that old so 'millions' super fast probably isn't an option. Mac Pro certainly isn't going to do those kinds of numbers. ) 20M M2-sized dies really isn't that much at 45K/mo run rates. If just wait until after the initial A17 demand bubble build they can weave those in spread out over several months. [ It is Digitimes though so 45k may be some wonky number. At 25K/mo still wouldn't need to split much if did larger M-series modules in the iPhone "off season" before the May-July pre-release demand bubble. A 45K/mo rate out of N3E with fewer steps would be more believable. ]
20K Extremes with less than 2,000 wafers could have been done early in N3 ramp. I suspect Apple's plan was to finish off end of 2022 with a new Mac Pro that they could squeeze into the early N3 build up (which on 2018-2019 'plan' would happed earily in Q4 than it did.). Similar with the AR/VR headset. Again relatively low numbers means don't need 20K wafers/mo to get the product out the door.
Splitting these M3 family onto something separate than A17 doesn't really make much sense if Apple had both N3 designs mostly done. N3E starts too late to do much for iPhone. [ Maybe if the iPhone Max/Ultra is the only one that gets the new chip can cut the volume need to stockpile at launch way down. ]
85M is probably high for the total iPhone sales.
One estimate.
IDC, Morgan Stanley Q4 iPhone sales estimates revealed – Apple Must
the top end iPhone 14 variants are 65-80% of iPhone sales. The other models do sell in substantive volume (relative to units sales of all other cell phones) . If Apple keeps the "last years Max SoC " for the next round only really need to cover the Max (and if Apple tossed in a Ultra model on top). If there is a huge performance gap That will be more than 50% of iPhone 15 sales, but it will still have healthy competition with the more affordable A16 powered unit.
The A17 on N3-family should likely bring a smaller die than the A15/A16 if Apple uses FinFlex effectively. Wafer costs going up will also put lots of incentive for them to boost the number of good dies per wafer also.