It would be a really interesting story to find out why cutting edge tech like this isn’t being produced in the USA but in Taiwan.
To a large extent the technology is being produced in the USA and outside of Taiwan .
For example from about a year ago
“…. Today’s announcement isn’t just that our new Gate-All-Around (GAA) nanosheet device architecture enables us to fit 50 billion transistors in a space roughly the size of a fingernail. It’s not just that IBM Research’s second-generation nanosheet technology has paved a path to the 2-nanometer (nm) node. Or that we produced this breakthrough technology on a 300 millimeter (mm) wafer built at IBM Research’s semiconductor research facility in Albany, NY. …”
IBM Research’s second-generation nanosheet technology has paved a path to the 2 nm node, produced on a 300 mm wafer.
research.ibm.com
There are two major phases in rolling out the tech . Inventing the baseline tech and large scale manufacturing of products based on the tech . IBM is not in the wafer manufacturing business anymore , do continue to do research. So do several other labs in the USA. So pragmatically the is more ‘R’ than ‘D’ in the R&D mix .
There is real R&D going on in Taiwan, but the notion that they are the only ones ( or the only ones that matter ) is myopic read from a propri press release. ( IBM isn’t doing it all by themselves either. )
Why did companies in the USA seemingly drop the ball in not being able to offer this technology?
this tech has multiple names at different companies . “Gate all around “ “ nano sheets” , RibbonFET, MBCFET ,etc ( Samsung in Korea ( if recall correctly they have an intellectual property agreement with IBM ) , TSMC , and Intel )
The players in the 3D sheet fabrication game are outlined on this page.
www.anandtech.com
Because TSMC has had the fewest fab hiccups over the last 4-5 years some folks are picking them to be first to a high volume , tolerable defect process . That isn’t necessarily going to be true. This is a pretty big inflection point in manufacturing and everybody is going to need to move to new tools to lay things down more 3 dimensional.
Samsung is making stuff now in low volumes. they is a couple of years for them to figure it out. If they do then they would be past the teething phase . If do not they opens door for TSMC and Intel . Similar issues for Intel. If they do pathfinding now and latch onto a solution in next 1-2 years then they are back in the game . Pathfindin on “RibbonFET” doesn’t have to wait for the current FinFet ( Intel 4 and 3 ) to shave out their process. More expensive but can run development more in parallel .
But both Samsung and Intel would need to clean up track record of over promise and under deliver.
Samsung has rigid hierarchy issues. Right leader plugged into org at right places and they could execute well. Relatively less rigid , Intel also has issues org getting in the way of doing good engineering .
TSMC had hiccups when the first moved over to FinFET. Their inflection point transitions are not spectacularly clean either . wont be surprise if there is a slip from 2025 for high volume output ( not start up ) .