Apple Silicon Likely to Benefit as TSMC Aims to Launch 2nm Chips by 2025

[deconstruct60]

They’re the ones who pushed the nanometer narrative from the beginning. They used it to lure Apple away from IBM in the mid-2000s.

The whole fab industry was using nm in early 2000’s . When everyone was back on triple and high double digit ‘nm’ processes it was incrementally more uniform . The major problems started to happen when the transitor fabrication stopped being planar ( 2D ) and started into more elaborate 3D structures . finFET and upcoming Gate-All-Around or sheets/ribbon/etc stacked on top of each other

Intel said they could shrink their chips down to accommodate Apple’s design choices. IBM was having a very hard time getting the G5 to fit into an iMac, let alone a PowerBook.

that wasn’t about “shrinking” and more about haggling over wanting to pay Previously to G5 Apple was plitting orders for PPC chips over Motorola and IBM foundry services. IBM needed to get revenue volume with there Power and Z series chips. If those prod are largely paying the freight for the fab tuning process then things get skewed that way. If Apple had thrown lots of money on table early for wnat they wanted IBM had the skill sets to due something tuned more mobile.

Sony came to IBM on contract and got a SoC for PlayStation that worked pretty well . Previously I linked in an article about IBM demoing a “2nm” wafer a year ago . So the notion IBM didn’t have world class Silicon know how is suspect. Hey did and do . It is whether they want to focus it on an Apple product or not. Similar to whether Apple could build an XServe box update This year. They could but they will not.

It is a fork in road of interests . Apple didn’t want a clone ecosystem for a wider cost sharing foundation ( e.g., used propri chipsets as defacto dongles. Which leaves whole system costs higher for alternative operating system platforms. PPC at lower end was more tracked into high volume embedded systems ) and IBM has their own high revenue product priorities .

Apple was looking to lower costs by jumping onto a broad ecosystem to drive down cost for a long while. Just looking for right inflection point . Intel , EFI , heavy market shift to laptops, and IBM ( and Motorola dropping out ) all contributed to making that inflection point materialize .

 

[deconstruct60]

Intel has fabs in USA but could not keep up with the nm race. Taiwan and South Korea have simply become very skilled to make state of the art chips. Cost is also an issue.

the comment was made in context of ASML toold. TSMC and Samsung buy these from ASML ( in Europe) but elements of those tools have USA patents.

Also not the only tools needed for Gate all around . Most expensive though and a critical price. ( although as things get smaller most of tooling become a single point of failure if they don’t work well ) .

Applied Materials Enable 2D Scaling with EUV and 3D Gate-All-Around Transistors - News

Our selection of industry specific magazines cover a large range of topics.

siliconsemiconductor.net

TSMC , Intel , and Samsung have some custom tools they use but there are others besides just ASML that are needed.

when the ASML tool all by itself costs $0.5B each and you need 6-7 of them in a building that cost about as much to erect , the hourly wages of the workers isn’t a giant hurdle.

Samsung has had a plant in Austin TX for a long time.

Intel got more interested in boosting their stock price ( Billions in buy back instead of billions in leading edge fab equipment and/or broader/better pathfinding to new fab processes. Along with billions in dubious acquisitions … McAfee )

AMD also mostly bungled spinning out GlobalFoundaries to a group that wasn’t all that ‘clueful’ also. IBM paid GF to take their foundries off their hand ( not sell for gain … but actually pay in add to hand over the facilities ) .

 

[Rigby]

Intel should come up with a new marketing around the "nm Myth".

Well, they will switch from nm to Angstrom (1A = 0.1nm). Accordingly their version of "2nm" is "20A" (and is currently scheduled for 2024 with the Arrow Lake CPUs). But these numbers are only loosely related to actual structural sizes.

 

[X38]

Actually Intel is getting the first next generation High NA EUV from ASML which is the same company TSMC uses.

Intel and ASML strengthen their collaboration to drive High-NA into manufacturing in 2025 | ASML

Intel makes its first purchase order for ASML’s TWINSCAN EXE:5200 system, marking the next step on the path to EUV 0.55 NA (High-NA) introduction.

www.asml.com

Not just getting them first, but I’ve read that Intel has bought up all of the initial production of the next generation machines from ASML, and since there is nobody else left competing with ASML at the top end machines, that means Intel will probably be the exclusive supplier of chips using the next generation of leading edge production technology in the 2024/2025 time frame. If Intel starts providing foundry services and if Apple wants their chips to stay at the leading edge, it may well be that Apple ends up using Intel to fab their chips in a couple years or so.

 

[deconstruct60]

I wonder if a 2nm chip uses roughly half the energy of a 4nm one.

Probably not for Apple usages. There is a 24-34% reduction from N5 to N3 variants. (and that is only if skip the performance increases; keep clocks all the same or slower). Doubtful Apple gives up all of the performance bump.

A table here.

https://www.anandtech.com/show/17452/tsmc-readies-five-3nm-process-technologies-with-finflex

[Note: that N4p gets 22% so not really a huge shift if pick the 'best' N4 variant and then go down from there.

plain N4 and N5P are about the same.

N4 "lower" and N5P -10%

The chances get better mostly because the plain N4 is pretty close to plain N5. So closer to jumping from N5 -> N2. So the cumulative change is going to bigger.
]


The N5 -> N3E is 34% and N3E -> N2 30%

TSMC Unveils N2 Process Node: Nanosheet-based GAAFETs Bring Significant Benefits In 2025

www.anandtech.com

So if hold the clocks/frequencies constant and completely prioritize for power reduction could a little pass 50% ( 100 * (1 - .34 ) * (1- .3) = ~48 ( 52% reduction). ( partially because the way transistors are being formed is changing with N2. That "2nm" is more a marketing tool to denote making a progression as opposed to a measurement tool. But it is trying to connote indirectly savings so not totally wrong. )

But if start with the N4P max power savings. ( 32 - 22 = 10% from N4P to N3E ) : 100 * ( 1 - 0.10 ) * (1 - 0.30) = 63 (so 37% reduction)

Again, likely though that some chunk of that power savings is spent on clocking higher. When the system is semi idle, they will likely get some large relative savings, but not as much when cranking on computing something large and complicated. Probably will get more done for similar power using now. Especially in the larger laptops and desktops. (much bigger caches , more bursty clock speeds when appropriate , and more throughput... all leading to higher performance. )


Will get a M5 that beats the MP 2019 ( 6 years old at that point) on a wider set of workloads and lower quartile MP 2019 configurations.

 

[deconstruct60]

Not just getting them first, but I’ve read that Intel has bought up all of the initial production of the next generation machines from ASML, and since there is nobody else left competing with ASML at the top end machines,

If Initial production is 5 then that probably is not enough to stake out a grand empire.
They probably cost $0.6-0.7B (yes B billion) a pop so it isn't like the initial production run is going to be large double digits.

Intel has to put at least 1-2 in a 'lab' to figure out how to do large scale productions runs so if there were 3 left for a production fab, it isn't tons of through. More than they had previously, but not an 'empire' building amount.

If initial production run is 3 then even less empire building.

that means Intel will probably be the exclusive supplier of chips using the next generation of leading edge production technology in the 2024/2025 time frame.

Unless TSMC or Samsung work out a way to do Gate-all-around with non high-NA EUV tools. Samsung has a G-a-A with no high-NA tool at all. Sort of like how Intel brute forced 10nm++ - Intel 7 production with more tools and more multipatterning. Takes longer to make , so lmited on max volume (versus using better tools) but could offer something at volumes relatively lower than Intel's. That would break exclusivity, but not by much ; so prices would be quite high. .

And decent chance there is N3E++ process out if TSMC has to wait a bit for more fab tools.

If Intel starts providing foundry services and if Apple wants their chips to stay at the leading edge, it may well be that Apple ends up using Intel to fab their chips in a couple years or so.

I'm not going to be surprised if the initial customers for N2 / 20A are not either folks who build chips generally smaller than Apple (and have even large volume to offset costs) or folks who make much higher mark up processors in far lower volume. Pretty good chance that out of the first 10-12 machines that ASML doles them out somewhat evenly and that none of them have tools to do crazy large wafer starts. Either get more out of wafers ( smaller dies) or just pay more scarce wafers (for quite high margin product).


Volume wise, high-NA machines wouldn't make wide product , large volume impact for 18-28 months after ASML starts pumping them out.

 

[HiRez]

I'd love to get a 25%-30% battery life increase. The M1 MB Air is already very good, but a few more hours would be fantastic and would mean I could take it out for a full day with no worries about bringing a charger along.

 

[falainber]

What happens when they hit 1nm? Is it possible to go even smaller?

It's just a name that has nothing to do with actual sizes. They have many options. For example, they can go with -1nm, -5nm and then -1μm etc.

 

[falainber]

They’re the ones who pushed the nanometer narrative from the beginning. They used it to lure Apple away from IBM in the mid-2000s. Intel said they could shrink their chips down to accommodate Apple’s design choices. IBM was having a very hard time getting the G5 to fit into an iMac, let alone a PowerBook.

Well, back then the process names actually did have physical sense for they reflected actual silicon sizes. So, Intel was right to advertise their better process. This stopped when Intel released FinFet transistors (at 22nm). Ever since then process names lost any connection with the silicon sizes and foundries (TSMC and Samsung) overtook Intel in naming numbers because they release new processes way more often than Intel (and even when the actual size does not change the process name does whereas Intel used +,++, etc.)

 

[progx]

The whole fab industry was using nm in early 2000’s . When everyone was back on triple and high double digit ‘nm’ processes it was incrementally more uniform . The major problems started to happen when the transitor fabrication stopped being planar ( 2D ) and started into more elaborate 3D structures . finFET and upcoming Gate-All-Around or sheets/ribbon/etc stacked on top of each other.

that wasn’t about “shrinking” and more about haggling over wanting to pay Previously to G5 Apple was plitting orders for PPC chips over Motorola and IBM foundry services. IBM needed to get revenue volume with there Power and Z series chips. If those prod are largely paying the freight for the fab tuning process then things get skewed that way. If Apple had thrown lots of money on table early for wnat they wanted IBM had the skill sets to due something tuned more mobile.

Sony came to IBM on contract and got a SoC for PlayStation that worked pretty well . Previously I linked in an article about IBM demoing a “2nm” wafer a year ago . So the notion IBM didn’t have world class Silicon know how is suspect. Hey did and do . It is whether they want to focus it on an Apple product or not. Similar to whether Apple could build an XServe box update This year. They could but they will not.

It is a fork in road of interests . Apple didn’t want a clone ecosystem for a wider cost sharing foundation ( e.g., used propri chipsets as defacto dongles. Which leaves whole system costs higher for alternative operating system platforms. PPC at lower end was more tracked into high volume embedded systems ) and IBM has their own high revenue product priorities .

Apple was looking to lower costs by jumping onto a broad ecosystem to drive down cost for a long while. Just looking for right inflection point . Intel , EFI , heavy market shift to laptops, and IBM ( and Motorola dropping out ) all contributed to making that inflection point materialize .

Were you there? The G5 was a thermal nightmare for Apple to try and work in the PowerBook. Tim Cook said it would’ve been a miracle in thermal engineering in early 2005 when he was VP of Worldwide Marketing. The PowerPC 970fx was the rumored chip, but it wasn’t working out. Apple stayed quiet as they worked on making the switch.

PowerBook G5: Long Rumored, Never Produced | Low End Mac

lowendmac.com

The consoles played a tiny part in the switch, but it came more down to the products Apple wanted to make. The original MacBook Air in 2008 was Apple running with the new Duo line. The Xbox couldn’t run OS X without some crazy hacks, plus the PS3… it’s not the 970, Cell was a custom SOC reprieved from it, but shared very little commonality with it. Why do you think Sony is struggling to get PS3 games to emulate? Microsoft made the smart move to use the 970 as Apple had, but with some deviations in SOC design. They bought Connectix before Apple switched from PowerPC, plus they and Microsoft have a technology trade agreement; pretty sure they had access to Rosetta version 1.

 

[progx]

Well, back then the process names actually did have physical sense for they reflected actual silicon sizes. So, Intel was right to advertise their better process. This stopped when Intel released FinFet transistors (at 22nm). Ever since then process names lost any connection with the silicon sizes and foundries (TSMC and Samsung) overtook Intel in naming numbers because they release new processes way more often than Intel (and even when the actual size does not change the process name does whereas Intel used +,++, etc.)

More or less, but they can’t distance themselves from something they popularized. Intel already had egg all over their face, they don’t need to be swimming in more embarrassment.

 

[Glideslope]

TSMC="Thor God of Thunder."

 

[Prince134]

The same reason so many things are made in China etc. - it's cheaper.

In fact, you need to think the other way. Those are no cheaper. It's because USA are richer.

 

[svish]

2nm chips will be very powerful. But they are some time away. But even today the 5nm is really good!

 

[dmi]

Funny how they call it 2nm while the transistor size or the absolute distance between the transistors is no where near 2 nanometers.

It never was the transistor size or the absolute distance between the transistors, even when it was still being given in micrometers.

 

[name99]

To a large extent the technology is being produced in the USA and outside of Taiwan .
For example from about a year ago

“…. Today’s announcement isn’t just that our new Gate-All-Around (GAA) nanosheet device architecture enables us to fit 50 billion transistors in a space roughly the size of a fingernail. It’s not just that IBM Research’s second-generation nanosheet technology has paved a path to the 2-nanometer (nm) node. Or that we produced this breakthrough technology on a 300 millimeter (mm) wafer built at IBM Research’s semiconductor research facility in Albany, NY. …”

Introducing the world’s first 2 nm node chip | IBM Research Blog

IBM Research’s second-generation nanosheet technology has paved a path to the 2 nm node, produced on a 300 mm wafer.

research.ibm.com

There are two major phases in rolling out the tech . Inventing the baseline tech and large scale manufacturing of products based on the tech . IBM is not in the wafer manufacturing business anymore , do continue to do research. So do several other labs in the USA. So pragmatically the is more ‘R’ than ‘D’ in the R&D mix .

There is real R&D going on in Taiwan, but the notion that they are the only ones ( or the only ones that matter ) is myopic read from a propri press release. ( IBM isn’t doing it all by themselves either. )






this tech has multiple names at different companies . “Gate all around “ “ nano sheets” , RibbonFET, MBCFET ,etc ( Samsung in Korea ( if recall correctly they have an intellectual property agreement with IBM ) , TSMC , and Intel )

The players in the 3D sheet fabrication game are outlined on this page.

Intel's Process Roadmap to 2025: with 4nm, 3nm, 20A and 18A?!

www.anandtech.com

Because TSMC has had the fewest fab hiccups over the last 4-5 years some folks are picking them to be first to a high volume , tolerable defect process . That isn’t necessarily going to be true. This is a pretty big inflection point in manufacturing and everybody is going to need to move to new tools to lay things down more 3 dimensional.

Samsung is making stuff now in low volumes. they is a couple of years for them to figure it out. If they do then they would be past the teething phase . If do not they opens door for TSMC and Intel . Similar issues for Intel. If they do pathfinding now and latch onto a solution in next 1-2 years then they are back in the game . Pathfindin on “RibbonFET” doesn’t have to wait for the current FinFet ( Intel 4 and 3 ) to shave out their process. More expensive but can run development more in parallel .

But both Samsung and Intel would need to clean up track record of over promise and under deliver.
Samsung has rigid hierarchy issues. Right leader plugged into org at right places and they could execute well. Relatively less rigid , Intel also has issues org getting in the way of doing good engineering .

TSMC had hiccups when the first moved over to FinFET. Their inflection point transitions are not spectacularly clean either . wont be surprise if there is a slip from 2025 for high volume output ( not start up ) .

That's one analysis.
Another analysis is that TSMC's success vs Intel's failure is not about hiccups over the past few years, it's about a basic conflict in how businesses operate in the two countries.

TSMC is run as an engineering operation, by engineers, according to engineering principles. Changes are made cautiously, one step at a time, and nothing is announced until it is very certain.

Intel (for the past 20 years or so) has been run as an advertising company. The most important thing is to make glitzy announcements that sound good and boost the stock price. TSMC cautiously states what the process *may* look like in two years; Intel manically announces what they will be doing ten years from now.

This has consequences. Intel's search for big announcements (rather than small ongoing improvements) is probably what led to the many missed deadlines of 14nm, then the disaster of 10nm. Likewise the insistence on publicly stating the roadmap years in advance makes it very difficult to change plans when that something unexpected means the roadmap is no longer ideal.

Has this changed with Pat Gelsinger? The Intel fans will say yes. I see no evidence. Arc is delayed. SPR is delayed. There was no honest communication around either of these. The ten year roadmaps are still being created and marketed. IF the i4, i3, 20A, 18A cadence is actually met I'll admit I was wrong -- but I fully expect that to engage in some combination of slippage, legalistic language ("technically we did manufacture something using i3 in H2 2023, even though we only sold four of them, to a company in North Korea so, sorry, you can't actually buy and benchmark them"), and redefinition of exactly what the node does (*some* process called 20A will be used; whether it corresponds to what Intel claims 20A to be right now, well...)

As for Samsung, well, they were doing fine until the started engaging in Intel-style practices a few years ago -- started laying down crazy roadmaps into the future, started imagining that marketing claims ("first to 5nm!", "first to GAA") were somehow more important than actual engineering.
But marketing, and selling the future, is a hell of a drug – once you're addicted, it's very very hard to get off. Witness Intel which has gone through at least two rounds of claiming to quit (as new CEOs came in), only to be back partying it up after just a few months.

 

[ccsicecoke]

We start all over again with Ångström, where 1 nm = 10 Å. The big question is how far physics will let us go. Molecular bonds are typically 1-2 Å in length so we can’t go smaller than that with ordinary matter.

quantum computer will dominate the world in few years before that

 

[SFjohn]

Considering an atom is 0.1 to 0.5nm, that's not going to happen.

Since it’s ALL marketing talk at this point, of course it will happen. 😂

 

[String]

Whatever the size they are still very fast and cool compared to the competition. That’s what matters.

 

[deffhaus]

Too bad China will own this technology in less than a year.

 

[NBAasDOGG]

It never was the transistor size or the absolute distance between the transistors, even when it was still being given in micrometers.

So what is it then? And why do they call it nanometers? (which has a very specific metric meaning!)

 

[Hessian]

I love me some pico, but I think tonight is a queso night.

That was cheesy.

 

[SFjohn]

then we will have 999 pico meters to play with before reaching femtometers... and then attometers.....

Personally I prefer the Ångström measurements to pico meters. After 2nm go to 10 Å and it will start a 20 year marketing countdown from 10 Å to 1 Å… 😉

 

[progx]

1 hour of manpower in China - so far - costs a lot less than 1 hour of manpower in the USA. That's because the population there is way poorer than the average US citizens.
Personally, I hope that one day every worker will get the same wage independently of the country they live in.
But so fare there will be inequalities on this planet, that will remain a dream, and the super rich will remain such.

Another thing we don’t do in the US, teach basic engineering to children. Most have to wait for middle or high school here before they can take it, but not all schools across the country offer any longer either. China is even teaching kids how to write code at a young age too, you’d be lucky if any high school in the US offers it as an elective.

 

[Kabeyun]

That was cheesy.

I din’t know what you’re taco’n about.