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Yeah. But I don’t remember that they were planning on any products with 3nm this year, where they?

Several years ago ( pre 2021 ) Intel has had some "Plan B" ( 'in case Intel 4/3 don't work" options to do N3 ). Around 2019 there could have been fanciful Intel roadmap that had Arrow Lake arriving late 2023. But how accurate were Intel's plans back then? And if the discrete graphics had flawless flowed through its progression.

Plans since Gelsinger came back ( in 2021)? No, not really. But that is kind of late in the game where are suppose to start queuing up for wafer start reservations.
 
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Alternatively Intel must be thinking to themselves that TSMC are such an unreliable manufacturer. TSMC failed to deliver on their promises for 3nm both in terms of time and quality.

The most premium customer (Apple) in the world decided to buy their entire 3nm 2023 output, but sure let’s call TSMC unreliable
 
Good for Apple!
qs for Intel, they played TSMC 2 or so years ago when supposedly they wanted like 50% or so of the initial 3nm TSMC capacity, that will not bode well in the long run for them, but then again, supposedly they're making progress on their own ...
 
Alternatively Intel must be thinking to themselves that TSMC are such an unreliable manufacturer. TSMC failed to deliver on their promises for 3nm both in terms of time and quality.
ha ha, over the pst 5 or more years TSMC has clearly beaten Intel from a technology (node shrinking) perspective ... it's Intels design changes that caused their tracking back ...
 
It would seem odd for consumers to celebrate monopolies.

It is not a monopoly is consumers leave items on the store shelves. If TSMC has capacity for 80K and Apple is only buying 65K then there is 15K capacity just laying there doing nothing. Monopoly would be buying 75-80K when there is a 80K cap. Perhaps if the 80K was fixed in stone as the forever upper limit. But that too also isn't likely a long term constraint either.

Apple isn't buying all the capacity. They far more so the only buyer. That is a huge difference. Apple will have to compete harder for N3E. N3B is more expensive and it takes much longer to 'make'. If your logistics chain isn't 'just right' and demand extremely easy to predict/project ( and uniform ) then N3B far more risky process to use than N3E. Lots of folks are just skipping it for economic reasons. That will just put more competitive pressure on N3E wafers.

Most of the TSMC infrastructure for making N3B or N3E is the same. ( N3E just spends less time inside the machines . N3B uses "multipatterning" , so it takes multiple passes to get things 'printed' on the wafer. Therefore substantially more time to process. ). TSMC can produce more finished output with a fixed set of machines from N3E than they can from N3B. That is why it is substantively cheaper and more responsive to wafer start/stop adjustments ( to control finished product inventories).
 
Alternatively Intel must be thinking to themselves that TSMC are such an unreliable manufacturer. TSMC failed to deliver on their promises for 3nm both in terms of time and quality.

Errr... Intel hasn't hit a long term roadamp deadline in 4-5 years. Xeon SP 4 ( Sapphire rapids was about 12 months late due to a bunch of bloppers. )

" Intel's Sapphire Rapids has been plagued with rumors that its design/verification missteps led to 12 steppings for some configs (an unnaturally large number — most chips see three steppings at most). Naturally, that led to severe production delays and missed launch dates. ..."


closer to TSMC thinking that "garbage in, garbage out". Over past 3-4 years Intel has done a lot of throw everything at the wall in shotgun fashion and see what sticks design work. ( 'late in the game' backporting to 10nm design back to 14nm , mash big little but drag along AVX-512 subsystem can't turn on , etc. ) . Too much effort of trying to do everything for everybody and not crossing t's and dotting i's on a focused subset.

Some rumors that even some of the upcoming Meteor Lake hiccups are far more where the fab folks not tasked with cleaning up goofs at the design level.


Intel's Arrow Lake was tied to TSMC N3 in various ways , but Intel hasn't even gotten its predecessor out yet. It is a late 2024 product. That isn't even aggressive scheduling against N3E rollout. [ Probably was a fantasy land roadmap where a Battlemage N3 discrete GPU was in 2023 also , that was disconnected from reality too. ]

Intel is turning the corner on getting pulling in ambitions to match their capabilities to get products coming out on time . 2024 products probably will come on schedule because they have cancelled the 'bridge too far' variations.
 
Good for Apple!
qs for Intel, they played TSMC 2 or so years ago when supposedly they wanted like 50% or so of the initial 3nm TSMC capacity, that will not bode well in the long run for them, but then again, supposedly they're making progress on their own ...

If the initial capacity was 20K/month wafers then 50% would be around 10K. If the longer term plan was to ramp N3B to 80K and keep orders at the same levels ... ~ 13%. If Intel is going 10K early on and Apple is only doing 10K early one ... neither one of them is extremely high volume. It does help spread out the 'pipe cleaning' costs over two organizations. More data improves the QA process. If loose 50% of early data then also negatively impacts time to QA improvements also. ( fewer sampes ... less feedback ... slower process. Throw on top the wafer processing time also takes several weeks long and feedback process even slower. )

"played TSMC 2 or so years ago" is a bit of a overeach. 2 or so years ago there pandemic driven crisis of wafer availabilty. Everybody was trying to lock down wafer starts on "snooze , you loose" treat the automakers found themselves in when they dumped wafer starts ( because thought weren't going to sell cars ) and then couldn't find any start slots when turned out they did need inventory. TSMC complained that everyone was inflating their reservations.

Intel squatting on a sizable set of wafer start did help them competitively (AMD , Nvidia , etc weren't going to get them while Intel had their own internal fab that few outside designers wanted access to those wafers. ). But Intel also grossly underbought EUV fab equipment. It really wasn't about whether Intel "7" ( 4/3 ) worked or not. Intel just couldn't do very high volume at EUV levels anyway no matter what their fab recipe was or how well it worked. Intel threw lots of money at buying substantially more of the previous gen fab machines ( for better or worse. ) and at dividends to keep the stock price high instead at equipment they would eventually need to be competitive in EUV foundry market space. ( and spending too much time listening to 'Wall Street' chants to go fabless. Helping to rationalize the crippling long term infrastructure underspend greed. )

And the 'green field' discrete graphics path Intel was following was all external. That wasn't 'played' notion at all. The underspend on EUV eqiupment put any dGPU product line that got decent traction on TSMC ( or Samsung if TSMC turned Intel down) for more than several years. [ turned out Intel goofed on drivers and design , but don't really know it won't work when lining up early slots. ] How many GPU chips they were going to need in a "brand new" business would be very hard to accurately project so Intel very likely always was going to outsource that production to 'on demand' outsourced fab work. If need a lot less , cancel wafers ( which is cheaper than eating extra fab equipment can't use) . If not more , order more (and hope can round up wafer slots someone else happens to no be using).
 
Just stop with the 'monopolist' drivel. You don't know what the word even means.
We’re talking about TSMC, not Apple. They have very little actual competition, meaning people who can compete with their products.
 
If the initial capacity was 20K/month wafers then 50% would be around 10K. If the longer term plan was to ramp N3B to 80K and keep orders at the same levels ... ~ 13%. If Intel is going 10K early on and Apple is only doing 10K early one ... neither one of them is extremely high volume. It does help spread out the 'pipe cleaning' costs over two organizations. More data improves the QA process. If loose 50% of early data then also negatively impacts time to QA improvements also. ( fewer sampes ... less feedback ... slower process. Throw on top the wafer processing time also takes several weeks long and feedback process even slower. )

"played TSMC 2 or so years ago" is a bit of a overeach. 2 or so years ago there pandemic driven crisis of wafer availabilty. Everybody was trying to lock down wafer starts on "snooze , you loose" treat the automakers found themselves in when they dumped wafer starts ( because thought weren't going to sell cars ) and then couldn't find any start slots when turned out they did need inventory. TSMC complained that everyone was inflating their reservations.

Intel squatting on a sizable set of wafer start did help them competitively (AMD , Nvidia , etc weren't going to get them while Intel had their own internal fab that few outside designers wanted access to those wafers. ). But Intel also grossly underbought EUV fab equipment. It really wasn't about whether Intel "7" ( 4/3 ) worked or not. Intel just couldn't do very high volume at EUV levels anyway no matter what their fab recipe was or how well it worked. Intel threw lots of money at buying substantially more of the previous gen fab machines ( for better or worse. ) and at dividends to keep the stock price high instead at equipment they would eventually need to be competitive in EUV foundry market space. ( and spending too much time listening to 'Wall Street' chants to go fabless. Helping to rationalize the crippling long term infrastructure underspend greed. )

And the 'green field' discrete graphics path Intel was following was all external. That wasn't 'played' notion at all. The underspend on EUV eqiupment put any dGPU product line that got decent traction on TSMC ( or Samsung if TSMC turned Intel down) for more than several years. [ turned out Intel goofed on drivers and design , but don't really know it won't work when lining up early slots. ] How many GPU chips they were going to need in a "brand new" business would be very hard to accurately project so Intel very likely always was going to outsource that production to 'on demand' outsourced fab work. If need a lot less , cancel wafers ( which is cheaper than eating extra fab equipment can't use) . If not more , order more (and hope can round up wafer slots someone else happens to no be using).
there were plenty "reports" (even here on MR if I recall) telling us that Intel bought all the 3nm capacity (there were reports of Gelsinger visiting Taiwan/TSMC to ensure of that), and at the time it was clearly for the GPU (Arc) and that whole thing went south, plus they were supposedly moving CPUs to TSMC too, which was bogus to begin with ... if Intel cannot fill their own fabs with their own products - they'd be losing money rather quickly.
And for EUV, Intel thought they didn't need it (for years) and that turned out to be their fatal mistake, and now they are playing catch up ...
And for their foundry efforts, well, not much happening as of yet ...
 
ASML machines to make the 3nm prints are 200 million dollars each. Return on investment is 90 days…
 
We’re talking about TSMC, not Apple. They have very little actual competition, meaning people who can compete with their products.
And not having effective competitors is not a monopoly either. A superior product that no one else has been able to duplicate is NOT a monopoly. Now if TMSC could be shown to be actively preventing other chip manufacturers from competing that would be different. But otherwise having superior technology that others have failed to catch up to does not mean it's a monopoly.
 
Chances are that you browse MacRumors from a TSMC-powered device, and have no option for seeking an equivalent without TSMC.
That sums up pretty clearly the meaning of "monopolist".
No, that's not a monopoly either. If there's no equivalent technology because other manufacturers have not been able to catch up that's their problem. Your assertion implies TMSC should be forced to teach other manufacturers how to duplicate their technology so they can 'compete' against TMSC. That's nonsense.

Finally, a monopoly is not illegal in and of itself. For years people have been trying to label Apple as having a monopoly over its own market because no one else can manufacture a Mac. Courts have never allowed that kind of argument to get any traction at all. So I stand by my opinion that tech blog forum commenters throw the words monopoly and monopolist around willy-nilly as pejorative invectives against the likes TMSC and Apple. It's nonsense.
 
We're two years and nine months out from initial M1 device sales, and Apple is still shipping them in new (and perfectly fine from a perf perspective) products.

Will they still be selling A17/M3 chipped devices in October of 2026? I hope they rev the 11" or 12" form factor by then.
 
First of all the process isn't even 3nm. That's the size of the FinFET. And with post silicon designs will be discussion picometer designs. Of course those will be in the hundreds of picometer in size. For example, 999 pm, not to be confused withy evening time. Or we'll continue to see .999nm, all the way .990nm over the course of a few decades. After all, we'll soon be dealing with 3D stacked designs.
3d stacking is the way to propell chip tech forward once they reach the node limit. Hopefully there will be design improvements to make it more efficient than what amd is doing
 
The new marketing term will be picometers. The challenge for the marketing team will be what number to add in front of "pm". Too small a number will make it sound like a clock time. Too big a number and people will think there is a backwards step.

After all, if you're at "3nm", who wants to go back to, say, "100pm" when "3nm" is clearly smaller than "100pm", eh?
Yeah, just like people can't understand what's happening when upgrading from 512Gb to 1TB ;)
 
Apple's done this before when Samsung made Apple's market monopoly possible with MP3 players when they swallowed up nearly all NAND memory for their iPods.

Greed is celebrated from Apple supporters, it's evident even in THIS THREAD RIGHT NOW.

Yeah. Wrong.

At one point Apple bought up at most about 25% of the world’s NAND capacity by prepaying (investing) billions of dollars. They did so because they were moving all their products (including Macs which required a lot more storage than the iPod) away from disk-based storage to NAND. They were also working on the iPhone and iPad, so they knew they’d need a huge stock pile of NAND memory. That’s not greed, it’s common sense; Business 101.

However, Apple did originally buy up the entire supply of 1.8” hard drives from Toshiba.
 
Is Apple buying up all 3nm to prevent other companies from utilizing those chips, or is Apple buying up all 3nm chips because they truly see the demand for their own products? As far as I was aware I didn't think any of the other brands had need for 3nm this year. I could be wrong.
It's in the article, the title is misleading. Apple is the only one ordering 3nm for this year, so even their reduced order makes up to 100%.
 
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First of all the process isn't even 3nm. That's the size of the FinFET.
I'd be interested to see a source for that. According to https://semiengineering.com/transistors-reach-tipping-point-at-3nm/ , the fin width for 3 nm nodes is 5 nm:

"When the fin width for finFETs reaches 5nm (around the 3nm node), the contacted poly pitch (CPP) reaches a limit of roughly 45nm with a metal pitch of 22nm. CPP is the distance separating the centers of adjacent gate contacts."
 
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Intel's lack of orders means TSMC's sales of 3nm chips will be significantly lower this year. While TSMC is still expected to experience significant growth in the fourth quarter as it starts mass producing 3nm chips for Apple's needs, they too have been downgraded, according to DigiTimes' industry sources.

The report suggests TSMC's 3nm process output may be reduced to 50,000-60,000 wafers monthly in the fourth quarter, down from the 80,000-100,000 units previously anticipated, due to a cutback in Apple's orders. The current monthly output of TSMC's 3nm process is estimated at approximately 65,000 wafers, the outlet's sources said.
Is that really the case? Earlier statements by TSMC said they couldn't make enough chips for Intel + Apple anyways. If so, it may be that losing Intel won't reduce production, it will just reduce demand to match production.

"As our customers’ demand for N3 exceeds our ability to supply, we expect N3 to be fully utilized in 2023, supported by both HPC and smartphone applications."
--TSMC CEO C.C. Wei


"The growing challenge of smaller processes has seen even TSMC struggling to achieve the necessary yield rates for this year’s iPhone lineup. Back in April, the company said that it wasn’t able to keep up with demand for 3nm chips.

However, with reduced Apple orders, and Intel orders postponed, it now seems the company will be able to deliver all the 3nm chips needed this year."
 
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