No it's only work like that if the name represented a single dimension of the transistors which they don't. Tsmc is putting 3nm's density at about 1.7x 5nm let alone 4nm. Additionally, they're reporting a 15% higher frequency at the same power vs 5nm or 25% lower power at the same frequency vs 5nm. Pretty underwhelming. 4nm was said to be +5% frequency or -10% power vs 5nm so it's actually at about ~15% less power than the a16's process node. Tsmc's N3E is the real 3nm process as it actually has different transistor dimensions and isn't just a refinement. TSMC says N3E can do about 20% higher frequency at the same power or 35% less power at the same frequency vs tsmc 5nm so there's more of ur real gain.
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Apple to Buy TSMC's Entire Supply of 3nm Chips for 2023
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You're confusing some things here:No it's only work like that if the name represented a single dimension of the transistors which they don't. Tsmc is putting 3nm's density at about 1.7x 5nm let alone 4nm. Additionally, they're reporting a 15% higher frequency at the same power vs 5nm or 25% lower power at the same frequency vs 5nm. Pretty underwhelming. 4nm was said to be +5% frequency or -10% power vs 5nm so it's actually at about ~15% less power than the a16's process node. Tsmc's N3E is the real 3nm process as it actually has different transistor dimensions and isn't just a refinement. TSMC says N3E can do about 20% higher frequency at the same power or 35% less power at the same frequency vs tsmc 5nm so there's more of ur real gain.
1) There is no "4 nm". TSMC's confusingly-labeled "N4" chips are just a refinement of their 5 nm process.
2) All TSMC's N3 chips are on their 3 nm process, which is qualitiatively different from their 5 nm process. It's not just the N3E that qualifies there.
[And yes, as you said, "3 nm process" and "5 nm process" don't refer to actual dimensions; they are marketing labels.]
No it's only work like that if the name represented a single dimension of the transistors which they don't. Tsmc is putting 3nm's density at about 1.7x 5nm let alone 4nm. Additionally, they're reporting a 15% higher frequency at the same power vs 5nm or 25% lower power at the same frequency vs 5nm. Pretty underwhelming. 4nm was said to be +5% frequency or -10% power vs 5nm so it's actually at about ~15% less power than the a16's process node. Tsmc's N3E is the real 3nm process as it actually has different transistor dimensions and isn't just a refinement. TSMC says N3E can do about 20% higher frequency at the same power or 35% less power at the same frequency vs tsmc 5nm so there's more of ur real gain.
the SRAM/cache of N3E is the SAME SIZE as N5. Throwing broad congratulations at this as a major different transistor dimensions over N5 is exercise at cherry picking. For a very large , substantive chunk of the die it won't be.
N3E is making things a bit bigger on average than N3B. TSMC's reduction numbers are by using a mix of TriFlex on a standard Arm core impelmentation. Some of that is changing the TriFlex mix (if not the implemetnation objectives).
N3B 'problems' are partially because TSMC changed the dimensions a bit too far and have to do a variety of double pattening gyrations to cover all of what N3B tries to cover. N3E is walking back closer to what the that initial generation EUV fab machines can actually do. N3E prints 'bigger'.
Neither one is 'the real 3nm'. N3B appears to be a 'dead end' though. Likely won't have design logic compatible 'successor' updates. N3E is the lead of a broader family of N3 options. That family of options is 'real ' .
P.S. N3P is probably going to be something like a 'cleaned up' N3B (where get some broader density increases). ( but probably design rule compatible with N3E).
I know how both of those work. N4 is a refinement of n5 yet it provides an uplift despite keeping the same transistor dimensions, I never said otherwise. Intel 7 from intel 10nm did the same thing yet it still provided an iso power and iso frequency improvement just like n4 did vs n5.You're confusing some things here:
1) There is no "4 nm". TSMC's confusingly-labeled "N4" chips are just a refinement of their 5 nm process.
2) All TSMC's N3 chips are on their 3 nm process, which is qualitiatively different from their 5 nm process. It's not just the N3E that qualifies there.
[And yes, as you said, "3 nm process" and "5 nm process" don't refer to actual dimensions; they are marketing labels.]
Also, just because I said n3e is the real 3nm doesn't mean I said the original n3 is just a refinement of n5. The objective truth however is that you can't just migrate the n3 node to the n3e node like a typical refinement such as n5 to n4 or intel 10 to intel 7. It is a legitimately very different node
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Real as in what it was supposed to be as you've outlined they messed up with n3b and had to walk it back. N3e is what n3b was meant to be is why I used the term "real". Ofc nothing is truly 3nm when every one of their transistors dimensions is roughly an order of magnitude greater than the name.the SRAM/cache of N3E is the SAME SIZE as N5. Throwing broad congratulations at this as a major different transistor dimensions over N5 is exercise at cherry picking. For a very large , substantive chunk of the die it won't be.
N3E is making things a bit bigger on average than N3B. TSMC's reduction numbers are by using a mix of TriFlex on a standard Arm core impelmentation. Some of that is changing the TriFlex mix (if not the implemetnation objectives).
N3B 'problems' are partially because TSMC changed the dimensions a bit too far and have to do a variety of double pattening gyrations to cover all of what N3B tries to cover. N3E is walking back closer to what the that initial generation EUV fab machines can actually do. N3E prints 'bigger'.
Neither one is 'the real 3nm'. N3B appears to be a 'dead end' though. Likely won't have design logic compatible 'successor' updates. N3E is the lead of a broader family of N3 options. That family of options is 'real ' .
P.S. N3P is probably going to be something like a 'cleaned up' N3B (where get some broader density increases). ( but probably design rule compatible with N3E).
Real as in what it was supposed to be as you've outlined they messed up with n3b and had to walk it back. N3e is what n3b was meant to be is why I used the term "real". Ofc nothing is truly 3nm when every one of their transistors dimensions is roughly an order of magnitude greater than the name.
N3E isn't going to be what N3B was suppose to be. N3P might. N3E is backslide on N3B primary objective. If you "walked back" the implemetation , how can it achieve what it was trying to do? N3E will be "good enough", but it is doing something different. It wasn't what was 'meant to be' ; TSMC moved the goal posts.
N3E should make TSMC more money. It is a more monetarily effective use of the fab infrastructure that TSMC has bought. In terms of the objective of making a large pile of money, that is what what N3B was "meant to be". That is probably a goal match.
N3E is highly likely going to last longer. Decent chance N3B will be 'dead' in 2-3 years. 'Real' isn't a good connotation for that. Longer lasting doesn't really make it more genuine. N3E will be coupled to a longer set of N3-plus-some-other-suffix variants. But that doesn't make N3B 'fake'. N3B is going to be just as instantiated as the other N3-family variants are. 100's of thousands of wafers processed isn't 'fake'.
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