Thanks so much for the info above!
Do you know if there's any credibility to the M3 Ultra Studio using N3P instead of N3B and then another refresh for the Macbook Pro lines late this year / early next year with N3P as well?
Unlikely. First, if the Ultra is the 'top' of the M3 family line up , then very high chance that it is just two M3 Max dies stuck together like last time. Hence the major components of the Ultra already shipped back in 2023 which is far before the N3P would have been in high production.
Second, N3B design rules are not compatible with N3E. So the processor would have to be relayed out (re spin). So even if Apple decided they did not want to use two M3 Max dies to compose the Ultra .... That isn't cheap. The overhead costs would be very high to decoupled the Ultra from the rest of the M3 line up.
There are some rumors that Apple may 're spin' the A17 into a N3E version (and perhaps change the number or keep it). That makes some sense in that Apple is probably going to sell two or three orders of magnitude more A17's than Ultras. N3B may not be a long term node at TSMC and if Apple wants to keep making A17's for 3+ years N3B isn't a good fit. ( The A-series is sold in more devices than just the one leading edge iPhone. It trickles down into multiple products that in term they sell many millions of. )
Third, N3E is more affordable to make , but it is also larger for elements like cache and I/O ( backslides all the way back to N5 footprint sizes). The larger the cache the more cost ineffective it gets ( the wafer costs more and not getting any more density for additional costs). For the top end M-series SoCs .. N3P makes more sense than N3E , but if later might as well be M4 (something > 3 ) .
N3E chiplets from AMD, Mediatek phone SoC dies , etc all of those are 1/3-1/5 the size of a Max die (and way way less than Ultra aggregate die sizes). Relatively, monster large dies... make less sense. N3P seems more tuned for those ( wouldn't be surprising for Nvidia to land on that very late in 2024. ).
I'm a bit confused because TSMC's roadmap contradicts this article as 2nm would be utilized right after N3P. You probably already know that they had originally planned on the N3B rollout in 2022 but got delayed by a year. Yields for the current N3B are still rumored to be ~50%.
For the processes that Apple is plausible to use N3P is right before N2. If talking about mentions of N3X , there is no plausible path there. N3X throws energy efficiency out the window. Apple isn't going to touch that with a ten foot pole. Most other consumer dies likely won't either (from AMD / Intel / Nvidia / Qualcomm) . N3S probably not either.
I suspect N3S is going to be for folks who have 'sticker shock' at N2 prices. I don't think Apple is going to be pressed about that issue either ( just pass along costs. Cost increases aren't going to come out of Apple's pockets. )
N3B did roll out in 2022. The rumors that N3B are still at 50% is likely just 'echo chamber' junk from 2022. I've seen other reports in later in 2023 that brush off those. There seems to be a who clan of folks who want to poo-poo N3B to crank up the hype train that N3E is going to be the super fabulous miracle that they previous hyped N3B was going to be back in 2022. N3B is a bit 'bad' more so because it is a 'dead end'. Have to shift to new design rules to do any incremental update. Unless have tons of volume to hide that overhead, it just isn't worth it.
N3B takes longer to make. So it took longer than usual to iterate to higher yields.
[ For a while there were rumbling that nobody but Apple was going to use N3B. In that context N3B would 'die' prematurely substantively faster to provide a deeper motivated push off of N3B quicker. I suspect another problem was that Apple was the only 3rd party eating up some of that early ramp costs and they balked at shouldering more of the load when Intel dropped out. That pragmatically slowed things down also because if Apple made TSMC 'eat' more bad dies , then the wafer throughput that TSMC would pick wouldn't be high either. So that would make the iterative improvement QA process take that much longer on top of the longer cycle. When everyone in a multiple person crew boat isn't rowing together ... the boat doesn't go as fast. There is noting inherently wrong with the boat. ]
This guy on YouTube does a good job of explaining the new N3B designs. He is not the one who theorized the new Ultra moving to N3P but he does also say that there may be a switch to N3E/P given the costs of N3B.
Yeah I wouldn't be shocked if Apple went N3B -> N3B -> N3P with A-series and N3B -> N3P with the M-series.
The A16 was N4 which the M-series didn't touch. N3B -> N3E -> N3P would work for A-series also.
Very good chance that Apple was one of the strongest advocates for N3B "too aggressive" approach to density. So Apple using N3B longer is a bit of eating the dogfood you asked for situation. Dumping it 'early' for the M-series doesn't really do much helpful.
Kind of depends if Apple wants to keep the A17 Pro around long term or not. If short term , then A18/A18 Pro on N3E could 'cover' the N3B -> N3E transition costs. Do some optimizations and bug fixes and take most of the 'win' out of lowering costs a bit and some power savings from the fab process increment. Mainly to get a long term "hand me down" A18 SoC. The design updates from N3E -> N3P much cheaper and had some more heft to architecture changes and get a M4/A19 out of that. (and roll out M4 before A19. )
Edit: I didn't see
your post on the previous page where you brought this up.
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