Apple's First M3-Powered Macs Likely to Launch in October

[John-Paul Hunt]

swap file.

 

[chucker23n1]

Apple’s M2 on the Mac mini uses the SSD for shared memory storage if you only have 8gb of unified ram. So does the SSD speeds impact the overall performance of the SoC itself here?

The SSD speed impacts I/O, and if you're swapping a lot, then that drags down perceived overall speed. It doesn't impact CPU. (I'm not sure what SoC means in this context. Neither the flash nor the RAM are in the SoC.)

Do you have a reference for this?

Sure. Run ioreg.

The SSD (and the NVMe controller) is on a bus called ANS. That connects directly to the Apple T600 I/O bus. The PCIe root sits next to that, not in front of it.

(Note that this also differs between M1 and M2. I think they changed the keyboard to sit behind SPI, not USB.)

On Intel and AMD chips, I/O between the ports&SSD and the chip is done via PCIe lanes. On the M series chips, they also use PCIe (v. 4.0) for I/O between the chip and the ports, so I assumed the I/O for the SSD uses PCIe 4.0 as well.

M series chips offer PCIe lanes, but the SSD doesn't use them.

I.e., they've already got PCIe I/O in place for the ports, so why not use for the storage as well, particularly since they're not doing anything with their storage that PCIe 4.0 can't handle?

You'd have to ask them, but my guess is better latency.

 

[theorist9]

Sure. Run ioreg.

The SSD (and the NVMe controller) is on a bus called ANS. That connects directly to the Apple T600 I/O bus. The PCIe root sits next to that, not in front of it.

Interesting, thanks.

I don't have an AS Mac to check, but if I did would I run this?:
ioreg | grep SSD

I was able to find almost nothing online about the ANS bus. I did a Google search for the following:
apple M1 "ANS bus"
...and got just 6 (!) hits, only two of which were relevant, and only one of which was in English:

linux-m1/drivers/pci/controller/pcie-apple-m1-nvme.c at master · corellium/linux-m1

Linux kernel source tree. Contribute to corellium/linux-m1 development by creating an account on GitHub.

github.com

According to it, the ANS is actually a coprocessor (so I suppose the "ANS bus" would be its bus), and the connection is CPU -> ANS -> PCIe -> SSD:
"M1 contains a coprocessor, called ANS, that fronts the actual PCIe bus to the NVMe device."

Sounds like you're saying that's incorrect.

What happens when PCIe 5.0 SSDs hit the market--will the ANS bus have the bandwidth to handle them, or will Apple need to upgrade the ANS bus to a new generation?

Relatedly, is there any way to determine the number of PCIe lanes afforded by the M2 Ultra? I ask because I'm wondering if the ports on the Ultra Studio are able to make use of all that bandwidth. If yes, then the Mac Pro, in spite its PCIe slots, would not offer any more total I/O bandwidth than the Studio (though the PCIe slots do allow higher single-interface bandwidth than the Ultra can offer with TB4).

 

[chucker23n1]

Interesting, thanks.

I don't have an AS Mac to check, but if I did would I run this?:
ioreg | grep SSD

I'd add at least `-i` to grep to be case-insensitive, and probably also something like `-B 10` to get ten lines before it. Which isn't enough to actually get you the tree up to that item. (There's probably some `ioreg` flag to get you the specific tree up to that object.)

I was able to find almost nothing online about the ANS bus. I did a Google search for the following:
apple M1 "ANS bus"

I believe there's an additional nitpick here that it's not technically a bus; it's more of a main-subnode architecture, I believe.

...and got just 6 (!) hits, only two of which were relevant, and only one of which was in English:

linux-m1/drivers/pci/controller/pcie-apple-m1-nvme.c at master · corellium/linux-m1

Linux kernel source tree. Contribute to corellium/linux-m1 development by creating an account on GitHub.

github.com

According to it, the ANS is actually a coprocessor (so I suppose the "ANS bus" would be its bus), and the connection is CPU -> ANS -> PCIe -> SSD:
"M1 contains a coprocessor, called ANS, that fronts the actual PCIe bus to the NVMe device."

Sounds like you're saying that's incorrect.

I doubt anything Asahi Linux says is incorrect.

Keep reading the comment:

* M1 contains a coprocessor, called ANS, that fronts the actual PCIe
* bus to the NVMe device. This coprocessor does not, unfortunately,
* expose a PCIe like interface. But it does have a MMIO range that is
* a mostly normal NVMe BAR, with a few quirks (handled in NVMe code).
*
* So, to reduce code duplication in NVMe code (to add a non-PCI backend)
* we add a synthetic PCI bus for this device.

The way I read it is: the flash chip(s) expect a PCIe bus (not being Apple-specific), but ANS merely pretends to offer one. Apple's SSD controller then uses the other ANS for the other side of the communication.

What happens when PCIe 5.0 SSDs hit the market--will the ANS bus have the bandwidth to handle them, or will Apple need to upgrade the ANS bus to a new generation?

I imagine whatever SoC adds PCIe 5 support also makes whatever changes may be necessary to ANS (run it at a higher clock?), if any. Since there's not much in the way of a protocol, let alone anything defined by an open standard, Apple can pretty much do that whenever they need.

Relatedly, is there any way to determine the number of PCIe lanes afforded by the M2 Ultra?

Not a lot.

I ask because I'm wondering if the ports on the Ultra Studio are able to make use of all that bandwidth. If yes, then the Mac Pro, in spite its PCIe slots, would not offer any more total I/O bandwidth than the Studio (though the PCIe slots do allow higher single-interface bandwidth than the Ultra can offer with TB4).

It doesn't (see above). The Mac Pro uses a switch to reuse lanes.

5 of the slots including both x16 ones are bottlenecked into a single x16 gen4 channel.

 

[theorist9]

The way I read it is: the flash chip(s) expect a PCIe bus (not being Apple-specific), but ANS merely pretends to offer one. Apple's SSD controller then uses the other ANS for the other side of the communication.

I'm not sure. The language isn't clear. For instance, the word "fronts" in the following....

"M1 contains a coprocessor, called ANS, that fronts the actual PCIe bus to the NVMe device."

...would typically means that it's CPU->ANS ->PCIe -> NVMe

Are you saying that, when you run ioreg, it unambiguously indicates the path is CPU -> ANS -> NVMe?

And have you (unlike me) been able to find any independent documentation of this on the internet? Usually one can find multiple hits on pretty much everything Apple, so this seems curious.

Not a lot.

It doesn't (see above). The Mac Pro uses a switch to reuse lanes.

Yeah, I saw that tweet previously. The Intel MP does the same thing: Like the AS MP, it doesn't have enough PCIe I/O to support all its PCIe connections at full bandwidth. The difference with the AS MP is that the discrepancy between slots and bandwidth is much larger.

Hector says the M2 Ultra has 32 PCIe lanes:

I'm not sure how many PCIe lanes the M2 Ultra's ports take up. If it's as follows, and if no PCIe lanes are needed for storage...

6 TB4 ports x 4 lanes/port = 24 lanes
10 Gbs Ethernet = 1 lane
HDMI 2.1 = 3 lanes?
UHS-II SXDC + headphone + 2 x 5 Gbs USB = 1 lane?

....then the Ultra can only make use of ~ 30 lanes, which would mean that the MP does offer more I/O, but only modestly so. Feel free to update the above with correct lane values if you have them.

It seems the real value of the MP is (a) the general ability to install PCIe cards without needing a separate box; and (b) the specific ability to aggregate I/O into a single fast connection. E.g., you could use up half of your PCIe lanes (16/32) on one of these, which would provide a (claimed) 208 Gbps data transfer rate, equivalent to more than 5 TB4 connections:

[If the claim is true, than that would provide a significant boost in I/O over the Ultra, since it would take 20 PCIe lanes to support 5 TB4 connections at full bandwidth; it sounds like when you have 4 PCIe lanes/TB4 port, some of the PCIe bandwidth goes unused. By aggregating those into a single higher-banwidth connection, you avoid that loss.]

HighPoint Launches Dual-Width NVMe Gen 4 AIC Series for Apple Mac Pro M2 Ultra | CdrInfo.com

www.cdrinfo.com

"HighPoint’s Dual-Width E1.S and M.2 NVMe AICs are the perfect High-performance storage solution for Apple’s new powerhouse. Designed for high-stress media, industrial and AI applications, SSD7749 series NVMe RAID AIC host bus adapters, are capable of delivering up to 28GB/s of sustained transfer throughput via a single PCIe Gen4 x16 slot, and double-this with a Cross-Sync configuration!"

 

[Elohim369]

Everyone's buying the M1 MBA as it looks much sleeker than the M2... hope they keep that around too. Also gold-pink - much better color, much prettier, than anything on the M2 MBA.

I think they will upgrade the 15" MBA alongside the 13 - Apple's strategy seems to be "ship it when it's ready". M3 will be ready

 

[JimmyG]

Ooh, here's an idea, Tim...

How about slapping some of those M3 chips into a 27" iMac chassis (like you did with the Mini and the Pro) to fill that gaping hole in your desktop line-up? D'oh!

 

[ric22]

Everyone's buying the M1 MBA as it looks much sleeker than the M2... hope they keep that around too. Also gold-pink - much better color, much prettier, than anything on the M2 MBA.

I think they will upgrade the 15" MBA alongside the 13 - Apple's strategy seems to be "ship it when it's ready". M3 will be ready

I liked the previous chassis designs of the Air and Pro a lot more- the Air was more comfortable on the lap or in bed, and the Pro was easier to pick up one handed.

 

[xbjllb]

Cmon Daddy needs a new M3 Mac Studio or Mac Pro.

 

[chucker23n1]

Cmon Daddy needs a new M3 Mac Studio or Mac Pro.

The M2 ones are literally three months old. Not happening.

 

[xbjllb]

The M2 ones are literally three months old. Not happening.

And from what I've been reading, not selling. I can wait.