I'd be interested in seeing how they made the blocks. I'm wondering
if they went to the extent of sputtering the layers together directly on
die (no TIM). And if so, how'd they manage it cost wise.![]()
Dunno about cost. User cost is usually mostly about volume. If Intel or
IBM make a billion of them they'll be cheap. Die fabrication, engineering,
and etc. is probably relatively the same as every other chip in any similar
class. I'd be surprised if it were much more.
As far as where exactly the layers are it's hard to say from that animation
but I don't think the silicon surfaces are modified at all. I think it's in the
ceramic packaging (or instead thereof rather). I get that impression anyway.

I guess we could look it up. IBM Power6 Hydro Cluster cooling.
I found this:
"IBM Research's Water Cooled Chips: Scientists at IBM's Zurich Research
Lab are working on the future of water cooling, brining cold water to the
hottest part, directly on the chip itself, and then capturing the water at its
hottest and piping it off the chip for re-use."
Basically the same thing as the video tho.

There's a blue one too.
I guess the pinkish salmon colored layer in this illustration is the silicon surface:
Then again this http://blogs.zdnet.com/BTL/?p=9031 makes it sound like it's
also integrated in the silicon itself maybe.
produced with current manufacturing methods except for the tools needed to etch
and drill the interconnections."
With all those layers of holes (what were there, like, 6 or something?) I also
wonder about pressure and flow.
Many articles and press sheets are saying that this is just the first step as well: "This
chip level water cooling is the first step in major advances IBM researchers have
planned for direct in-chip water cooled systems.", "The next step for IBM is to
optimize cooling systems for smaller chips and more interconnects."