G5 may not be what we've been expecting.

[mischief]

Modularity:

Although the cost of production would go up I'd love to see an Apple mobo with modular parts. Not just the processor, but the clock chip, HD Host circuitry, RAM slots as a daughterboard, etc.

I'd love to buy 1 case from Apple and swap parts for 10 years. I'd even be happy to buy the parts from Apple.

I have looked around on Moto's site and their component mobo parts make me salivate. Put an IBM 10Ghz bus controller chip on a Moto mobo and you'd have a PPC that'd leave any wintel machine wetting itself.

I have heard rumors to the effect that Apple will go to an all MP architecture. This means that for Apple to stay on target either they or IBM will have to acquire rights to manufacture with Altivec.

The line was described as having from 4 to 8 G5 processors. Adding Altivec and the 32 bar tech to IBM's 750FX G3 would give us a transitional chip quickly that could approach this model.

dpaxton, could you look over the "A New Vision" thread and comment please?

 

[dpaxton]

vision etc.

One would need to start with the common problems seen with our current hw and see what others have as solutions. Rapidio is a great way to get around the data bottlenecks on motherboard. Look at rapidio.org for configurations. At 512MB per link per sec. 8 would give 4 gigs throughput. Crossbar switches like the IBM chip is what the connectionist gurus of the 80's dreamed of. It would be nice to see the linux ppc guys allow all data I/O and message passing to cross this bus only in the machine. This would allow for nodes to handle I/O, processing, storage etc. PCI-X would become obsolete quickly but a cheap way for expansion with a quick bus that would be better than AGP. All of this could be implamented from a basic number of building blocks (inexpensive) to a large fine grained system. Discussion on cache sizes, ddr, bus width, number of AGP slots etc. would be reduced to a fewer number of variables since overall throughput has increased dramatically.

 

[mischief]

Bravo!

Thanx. That's very useful!

So a good start would be a 2/4/8 processor card with DDR slots dedicated per processor like a L4 cache sitting on an 8x Rapid I/O mobo running at (say) 250 with PCIx and modular comm and I/O port cards.

Use of Apollo G4's would make for swift development. Is there some way to do a clock-chip assembly that "adapts" to make the best of the attatched modules? Having modules that step their cycles up or down to optimize performance would make modularity much easier.

 

[dpaxton]

next

Processor card should be single with an improved mem bus for local card access. My thought normally dwellson the problem of the mem bottleneck. I do like the rambus system but they do use ten percent of the die for dual port and registers. With the current density I do think that this works but the raw I/O speed creates a power hog. I would like to see a dual ddr 16 bit bus on bga. At 333 to 512MHZ a 16 chip back card array would give two independent 128 bit buses. One used for I/O and the other to deliver a real time accurate instruction delivery of over 3 gigaops. A simplified cache internaly with an on chip bus at 256 bits would solve at least a few years of the bottleneck. No need to make reworked memory for rapidio. All on chip. Single cpu, boot flash and 16 mem chips. Cheap. All bus signals to and fro the card are rapidio. I would rather see a 16 pair rapidio for the cpu for a total of 8gig per sec. If all card slots and "bridge" chips are on the same 16 pairs for a dynamic routing option. This does elude to an on board dual port mem for ramdacs. Another single chips solution with the mutliple processors handling the grapics much faster than planed specialty chips and AGP buses etc.

 

[mischief]

How about this:

Mobo arranged vertically with slots for processor cards which are simply RAM and a G4 per card. From there the mobo is run from one of IBM's 10Ghz switch chip. It'd be like having a 10Ghz bus @64Bits wide.

 

[dpaxton]

possible

Moto is incorperating rapidio in processor. This would be cheaper than athe dual expensive chip option. The ibm chip has 32 in and 32 out. Each link is 2ghz, 512 MB per sec. totaling 16 GB per sec. With 16 mem chips each at 16 bits at 512 MHZ one attains balance assuming the individual card needs or can use all of the I/O. With muliple cards and data coming from drives etc. a load balanced approach like a normal network would be realized. This sytem would ideally allow for 16GHZ processors, 2GHZ mem ( I think I am dreaming about the mem ) with double clock radipio. If these actually could run at 50% alu utilization, 8 32 bit instructions can give a total of 1 teraop for the system. But this is a discussion of the cpu internals. Right now data bottlenecks are the biggest woe of all users. This spans from modem/broadband to the hard drive to our lousy cpu dram bus. It would be good though to use an off the shelf expensive option with all of the parts avaliable now. Linux driver it and then later do the asic work. If one goes that route then go ahead and use mips, majic ( love this one ) or any other core that could be used later in the asic.