IBM's PowerTune Technology

[Lanbrown]

Re: Oh the vents!

Originally posted by formasfunction
Call me crazy, and its possible that someone else already pointed this out in the pages and pages of posts, but has anyone taken a look at the new Xserve? Did you notice the huge vents on the front of it? Small animals could be sucked inside this thing if they scurried too close. And this is using the same processor that everyone is proposing for the PB. Granted, these things are designed to run balls to the wall 24/7, and some come with dual processors, two things that a PB won't have to deal with, but so did the previous Xserves and there were no signs of need for extreme cooling. Even though IBM has said that this chip COULD be used for laptops, I don't think that it WILL be used by apple until less extreme measures are needed, even taking into account the power management of the chip. I'll eat my hat and sell my G4 PB if we see G5PBs any sooner than 7 months.

Define seeing them before 7 months? I would expect to see them announced in June, shipping sometime later though. If you are talking of them shipping, then 7 months would be a good guess.

Others face it. Either Apple has buttoned down the leaks or there is nothing to leak. There were quite a few leaks about the G5 PM before it was released, even Apple let the cat out of the bag. There are some companies that nothing is leaked from and when there is a leak, it is usually done by the company to spoil an announcement from a competitor. I can't see Apple to going from quite a few leaks to none in a short amount of time.

 

[u2mr2os2]

Latency

Originally posted by Lanbrown
It will take at least one clock cycle to get that portion of the chip ready, now won't it?

But given the instruction pipeline, could it know it needs to wake up that portion before the instruction gets executed so there is no power-up delay?

 

[Rincewind42]

Re: Latency

Originally posted by u2mr2os2
But given the instruction pipeline, could it know it needs to wake up that portion before the instruction gets executed so there is no power-up delay?

The CPU should be able to determine that it needs to wake up a CPU unit at least 6 cycles before it is used. The 6 cycles is how long it takes for an opcode to get through dispatch on the PPC970. It takes at least 3 cycles (likely 4 or more) for an instruction to come in from fetch to reach decode, so it can be working on discovering what units are needed even sooner. And the CPU can determine what parts of an instruction unit can be turned down/off by watching instructions as they flow through the unit.

I have no idea how much of this information is used in PowerTune, so take it for what it is.

 

[Lanbrown]

Re: Re: Latency

Originally posted by Rincewind42
The CPU should be able to determine that it needs to wake up a CPU unit at least 6 cycles before it is used. The 6 cycles is how long it takes for an opcode to get through dispatch on the PPC970. It takes at least 3 cycles (likely 4 or more) for an instruction to come in from fetch to reach decode, so it can be working on discovering what units are needed even sooner. And the CPU can determine what parts of an instruction unit can be turned down/off by watching instructions as they flow through the unit.

I have no idea how much of this information is used in PowerTune, so take it for what it is.

In theory yes, but processors can make bad decisions and that's where the longer pipelines start to lose their momentum. With processors mainly waiting for data, shutting down any part of the chip or reducing the clock speed is a bad idea. It's a great idea for portables and desktops though; the effects are minimal on them.

 

[spankalee]

Re: Oh the vents!

Originally posted by formasfunction
Call me crazy, and its possible that someone else already pointed this out in the pages and pages of posts, but has anyone taken a look at the new Xserve? Did you notice the huge vents on the front of it? Small animals could be sucked inside this thing if they scurried too close. And this is using the same processor that everyone is proposing for the PB. Granted, these things are designed to run balls to the wall 24/7, and some come with dual processors, two things that a PB won't have to deal with, but so did the previous Xserves and there were no signs of need for extreme cooling. Even though IBM has said that this chip COULD be used for laptops, I don't think that it WILL be used by apple until less extreme measures are needed, even taking into account the power management of the chip. I'll eat my hat and sell my G4 PB if we see G5PBs any sooner than 7 months.

Well, not only will a PowerBook not be dual processor, but it's likely to run at speeds of 1.4 to 1.6 Ghz and have more aggressive power management settings. The 970fx uses a lot less power at 1.4Ghz than 2Ghz.

I expect to see the case be designed for better cooling as well. There might be some more obvious vents.

Another thing not mentioned yet is that the bus doesn't need to run an half the processor speed. There's options for 1/4, and maybe the 970fx has more multipliers. Having a lower bus speed is common in notebooks and would lower heat and save battery life.

 

[Rincewind42]

Re: Re: Re: Latency

Originally posted by Lanbrown
In theory yes, but processors can make bad decisions and that's where the longer pipelines start to lose their momentum. With processors mainly waiting for data, shutting down any part of the chip or reducing the clock speed is a bad idea. It's a great idea for portables and desktops though; the effects are minimal on them.

Well, that depends. If the time it takes to wake up the unit is 6 cycles or less, then it will be completely hidden by the dispatch time. If the pipeline needs to be flushed, then it will take even more time and the CPU should by then know what will be executed when. And if it is manly waiting for instructions to come from main memory, then it really doesn't matter what gets shutdown when because the latency from main memory through dispatch to instruction unit is on the order of a couple dozen cycles. PC3200 ram takes at least 5ns (10 cycles @ 2Ghz) to send the critical word to the CPU, the 970 looks at instructions 8 at a time so you need 2 RAM reads on a PMG5 which requires 7.5ns (15 cycles @ 2Ghz) to send from RAM to controller. Then tack on 3 cycles for fetch, 6 cycles for decode and you have 24 cycles from RAM to execution. And this is when everything is optimal. There is also bank switching in the RAM, translation on the system controller, packet transmission overhead between the controller and the CPU, and any number of stages that can be introduced between fetch and decode due to resource allocation issues.

 

[Snowy_River]

Re: Re: Re: Apple Engineering

Originally posted by Wendy_Rebecca
PHHHHHHHTTTTT!!!!!

That sound you hear is the coffee coming out of my nose. Apple IS THE MOST top-down organization ever, with King Jobs at the helm.

Honestly, did you think before you wrote that post?

Just because the organization as a whole is top-down doesn't mean that the project management end of things is. In fact, given that many studies have shown that rigidly top-down organizations are the slowest to innovate, the fact that Apple is regarded as a market leader in innovation would suggest that it's not all that rigidly top-down.

[Disclaimer] I have never worked for Apple's engineering department, nor have I ever spoken with anyone who has. I have no direct knowledge of what Apple's engineering structure is, and can only speak from external (distant) observation. [/Disclaimer]

 

[tiktokfx]

Originally posted by Lanbrown
Big deal? If you go with one thousandth of a second and 2200 processors, that is 2.2 seconds.

Actually if you go with .001 of a second and 2200 processors, that's .001 seconds of real time. 2.2 seconds of net computational time.

Also, it seems rather odd to randomly assume times like .001, which is 7 orders of magnitude greater than the cycle of a 2.5 GHz processor. A much more likely estimate of the time it takes to modify the speed of a processor would be the depth of the pipeline times the cycle time, which would be about .0000000064 seconds.

This also assumes that the tuning component of the processor is incredibly stupid and tries to scale back every chance it gets, instead of monitoring itself and seeing when it's useful to scale back.

As soon as a machine hits a point where it needs high availability of speed, it's going to remain there for a reasonable period. Truly high-activity servers will simply never scale back, if they don't have to. And that fraction of a second is not going to amount to much.

 

[aswitcher]

Re: Re: Oh the vents!

Originally posted by spankalee
Well, not only will a PowerBook not be dual processor, but it's likely to run at speeds of 1.4 to 1.6 Ghz and have more aggressive power management settings. The 970fx uses a lot less power at 1.4Ghz than 2Ghz.

I expect to see the case be designed for better cooling as well. There might be some more obvious vents.

Another thing not mentioned yet is that the bus doesn't need to run an half the processor speed. There's options for 1/4, and maybe the 970fx has more multipliers. Having a lower bus speed is common in notebooks and would lower heat and save battery life.

As long as the bus is significantly better than the current one which I have read in several places is the real bottleneck of the current design. Would a half gig bus be feasible?
😕

 

[Dave the Great]

<QUOTE>Originally posted by formasfunction
Call me crazy, and its possible that someone else already pointed this out in the pages and pages of posts, but has anyone taken a look at the new Xserve? Did you notice the huge vents on the front of it? Small animals could be sucked inside this thing if they scurried too close. And this is using the same processor that everyone is proposing for the PB. Granted, these things are designed to run balls to the wall 24/7, and some come with dual processors, two things that a PB won't have to deal with, but so did the previous Xserves and there were no signs of need for extreme cooling. Even though IBM has said that this chip COULD be used for laptops, I don't think that it WILL be used by apple until less extreme measures are needed, even taking into account the power management of the chip. I'll eat my hat and sell my G4 PB if we see G5PBs any sooner than 7 months.</QUOTE>

I don't think that is exactly a fair comparison - comparing the xserve to a pb.
The xserve, in addition to being able to use dual processors, also has 3 available drive bays for up to 750 GB, 2 full size PCI slots, up to 8GB of mem, more I/O connectivity, and is made so you can stack them on top of each other. This is why they have the vents.

I hope the G5 PBs will soon be launched!

 

[aswitcher]

Originally posted by Dave the Great
<QUOTE>Originally posted by formasfunction
Call me crazy, and its possible that someone else already pointed this out in the pages and pages of posts, but has anyone taken a look at the new Xserve? Did you notice the huge vents on the front of it? Small animals could be sucked inside this thing if they scurried too close. And this is using the same processor that everyone is proposing for the PB. Granted, these things are designed to run balls to the wall 24/7, and some come with dual processors, two things that a PB won't have to deal with, but so did the previous Xserves and there were no signs of need for extreme cooling. Even though IBM has said that this chip COULD be used for laptops, I don't think that it WILL be used by apple until less extreme measures are needed, even taking into account the power management of the chip. I'll eat my hat and sell my G4 PB if we see G5PBs any sooner than 7 months.</QUOTE>

I don't think that is exactly a fair comparison - comparing the xserve to a pb.
The xserve, in addition to being able to use dual processors, also has 3 available drive bays for up to 750 GB, 2 full size PCI slots, up to 8GB of mem, more I/O connectivity, and is made so you can stack them on top of each other. This is why they have the vents.

I hope the G5 PBs will soon be launched!

In desperation you could always strap a 17" screen, keyboard and a decent battery to an Xserve to get your dream X5 now...as long as your strong and fit 😛


Oh, just don't plan to use it naked, because then you'll have more to worry about than small furry creatures getting sucked into those huge vents 😀

 

[Analog Kid]

Re: Re: Oh the vents!

Originally posted by spankalee
Another thing not mentioned yet is that the bus doesn't need to run an half the processor speed. There's options for 1/4, and maybe the 970fx has more multipliers. Having a lower bus speed is common in notebooks and would lower heat and save battery life.

Which further degrades it's performance advantage against the G4...

Some folks seem to want a PB G5 just to have a G5 in a PowerBook. I don't know what Apple's thinking on this is, but I'm guessing they want a real advance with the new design-- not just an incremented G...

I still argue that the 90nm part is one piece of the puzzle, and we have to wait for the rest to fall into place. System controller is probably ready-- but I'd guess it's higher power than the G4 equivalent as well because of bus speeds.

Something needs to have a net power reduction to balance the power increases. PowerTune might help with the wind sprints, but I'm still guessing (note that-- guessing) that RAM is the gating item.

 

[Analog Kid]

Re: Re: Re: Re: Latency

Originally posted by Rincewind42
Well, that depends. If the time it takes to wake up the unit is 6 cycles or less, then it will be completely hidden by the dispatch time. If the pipeline needs to be flushed, then it will take even more time and the CPU should by then know what will be executed when. And if it is manly waiting for instructions to come from main memory, then it really doesn't matter what gets shutdown when because the latency from main memory through dispatch to instruction unit is on the order of a couple dozen cycles. PC3200 ram takes at least 5ns (10 cycles @ 2Ghz) to send the critical word to the CPU, the 970 looks at instructions 8 at a time so you need 2 RAM reads on a PMG5 which requires 7.5ns (15 cycles @ 2Ghz) to send from RAM to controller. Then tack on 3 cycles for fetch, 6 cycles for decode and you have 24 cycles from RAM to execution. And this is when everything is optimal. There is also bank switching in the RAM, translation on the system controller, packet transmission overhead between the controller and the CPU, and any number of stages that can be introduced between fetch and decode due to resource allocation issues.

Not much you can do in a few ns other than stop the clock... That was an effective power saver with larger feature sizes, but if you stop the clock at 90nm you're still leaking a lot of current. Not to mention that clock gating has been around forever and hardly deserves a new name like PowerTune.

Granted Intel does that all the time, but I have to think IBM has more class... (Not to mention they have a research facility that really does innovate).

There's been talk of "voltage islands" which I suspect means voltage gating. Turn the power off to parts that aren't being used so they don't draw dynamic current but also don't leak.

Intel has been scaling voltage with frequency since the early XScales, which is clever. They moved the same idea into Centrino, I think.

Problem with voltage scaling is you can't do it in nanoseconds... This is a 25W part which is pulling something like 12-15 amps. I can't imagine they can ramp that kind of current in 6 cycles. Lead and trace inductance will slow it down. IR drop in the chip would be too high...

I might be wrong on this-- the Intel chips pull a whole lot more current (4x?), and I know they have insane slew rate requirements. Maybe it can be done...

I'm starting to agree with the camp that says this will be used in notebooks that typically run one task at the speed of the user, and not used in servers/workstations that are going full tilt for days.

Guess we'll find out soon enough! =)

 

[Rincewind42]

Re: Re: Re: Oh the vents!

Originally posted by Analog Kid
Which further degrades it's performance advantage against the G4...

Yes, a G5 on a 500Mhz bus will not perform as well as a G5 on a 1Ghz bus. But it's a laptop - there will be compromises made. Unless Apple has discovered how to make dimensional pockets it's going to be really hard for them to put in more than 2 RAM slots (except maybe on the 17"). And if there are only 2 RAM slots, then you can't really require that RAM be installed in pairs, so your RAM (Even PC3200) wouldn't be able to keep up with a 500Mhz bus, let alone a 1Ghz one. At that point, the only advantage to a higher bus is bandwidth to other resources (which isn't a bad thing, but doesn't have as big a performance increase relative to RAM).

So my prediction remains a bottom end of 1.5Ghz/500Mhz bus. We'll see what we got when we get it 😀.

 

[Dave the Great]

Originally posted by aswitcher
In desperation you could always strap a 17" screen, keyboard and a decent battery to an Xserve to get your dream X5 now...as long as your strong and fit 😛

Why do you think I have been eating all that spinach and steak? 🙂

Oh, just don't plan to use it naked, because then you'll have more to worry about than small furry creatures getting sucked into those huge vents 😀

Oh man! I didn't think of that. Looks like I will have to wait for an actual G5 PB! 🙂

 

[spankalee]

Re: Re: Re: Oh the vents!

Originally posted by Analog Kid
Which further degrades it's performance advantage against the G4...

I don't get it...

Are you saying that a 1/4 multiplier is worse than the 1/8 multiplier used in the G4 powerbooks?

Some folks seem to want a PB G5 just to have a G5 in a PowerBook.

Well, because the G5 is a much better chip. I run my PowerBook to the max regularly, and I desperately need more horsepower. The G5 seems to be the only option for a drastic increase in performance, therefore I want a G5 PowerBook.

Simple, right?

 

[aswitcher]

Re: Re: Re: Re: Oh the vents!

Originally posted by Rincewind42
Yes, a G5 on a 500Mhz bus will not perform as well as a G5 on a 1Ghz bus. But it's a laptop - there will be compromises made. Unless Apple has discovered how to make dimensional pockets it's going to be really hard for them to put in more than 2 RAM slots (except maybe on the 17"). And if there are only 2 RAM slots, then you can't really require that RAM be installed in pairs, so your RAM (Even PC3200) wouldn't be able to keep up with a 500Mhz bus, let alone a 1Ghz one. At that point, the only advantage to a higher bus is bandwidth to other resources (which isn't a bad thing, but doesn't have as big a performance increase relative to RAM).

So my prediction remains a bottom end of 1.5Ghz/500Mhz bus. We'll see what we got when we get it 😀.

4 Ram slots would be sweet... Could go for a full two gig without breaking the bank... Or just a gig with cheap 256 sticks...

500Mhz bus maybe overkill then, perhaps it will be 400mhz like the Ram to save on heat and power but not to hold things up when its needed

 

[Rincewind42]

Re: Re: Re: Re: Re: Oh the vents!

Originally posted by aswitcher
4 Ram slots would be sweet... Could go for a full two gig without breaking the bank... Or just a gig with cheap 256 sticks...

500Mhz bus maybe overkill then, perhaps it will be 400mhz like the Ram to save on heat and power but not to hold things up when its needed

I don't know about 256 sticks being all that cheap really - from what I've seen you save only about $10 with a pair of 256s vs a pair of 512s, and that's only in PC2700 SO-DIMMs, standard PC3200 show no difference at all.

As for the bus, a 400Mhz would require 4x on 1.6 rather than 3x on 1.5. Also you would be slower than the RAM at that point (since the G5 bus has an overhead of about 10%). And if Apple does find a way to provide 4 slots, then slot pairing becomes more likely and we could see a 2x multiplier (although likely on slower RAM like PC2100 or PC2700).