Program instructions that take only one instruction on an Intel CPU, will have to be broken down into multiple instructions on RISC, running more instructions of course takes more time.
CPU designer here. I helped design many chips at AMD, as well as RISC chips (PowerPC and Sparc)
Your statement is wrong. Running more instructions (at least when we are talking about the scenario you are suggesting) doesn't take more time.
If I have an x86 instruction:
ADD [address], immediate
This has to:
1) load the contents of the address from memory into some sort of register
2) after that occurs, add the contents of that register to the immediate
Sure. That's one instruction. But it takes exactly the same amount of time, all else equal, as the following RISC instructions:
LOAD [address] -> register
ADD register, immediate
In fact, every x86 instruction is broken up into a set of "micro-ops" on any modern x86. So those complex instructions are broken into small, simple, instructions, and it takes the same number of passes through the pipeline to execute either way.
And with CISC you have the added penalty of having to perform the conversion to micro-ops, which adds lots of pipe stages (it requires a state machine, a ROM, extra tags to keep with the instructions to keep track of which ones are part of the same ISA instruction, etc).. Then, when you have more pipe stages, when you miss a branch prediction the penalty is much higher. So you need to build a more beefy branch prediction unit. All that takes extra area on the die, which means less power budget for everything else. etc.