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Program instructions that take only one instruction on an Intel CPU, will have to be broken down into multiple instructions on RISC, running more instructions of course takes more time.

CPU designer here. I helped design many chips at AMD, as well as RISC chips (PowerPC and Sparc)

Your statement is wrong. Running more instructions (at least when we are talking about the scenario you are suggesting) doesn't take more time.

If I have an x86 instruction:

ADD [address], immediate

This has to:

1) load the contents of the address from memory into some sort of register
2) after that occurs, add the contents of that register to the immediate

Sure. That's one instruction. But it takes exactly the same amount of time, all else equal, as the following RISC instructions:

LOAD [address] -> register
ADD register, immediate

In fact, every x86 instruction is broken up into a set of "micro-ops" on any modern x86. So those complex instructions are broken into small, simple, instructions, and it takes the same number of passes through the pipeline to execute either way.

And with CISC you have the added penalty of having to perform the conversion to micro-ops, which adds lots of pipe stages (it requires a state machine, a ROM, extra tags to keep with the instructions to keep track of which ones are part of the same ISA instruction, etc).. Then, when you have more pipe stages, when you miss a branch prediction the penalty is much higher. So you need to build a more beefy branch prediction unit. All that takes extra area on the die, which means less power budget for everything else. etc.
 
Howdy gnasher729,

I take it, that you are not a developer? It is very naïve to think that is all it takes is a quick re-compile to get a program to work on Apple Silicon, From a pure "will it run" idea, what you say is technically true. The program will open, but there is no guarantee that it will run very well. It may run very slow, or it may run too fast (not likely but possible), things that just worked before may cause the program to hang as it takes too long to execute, causing the OS to assume the program has hung. It is more complex than just a recompile. For simple applications, that do not require a ton of computational power to run, they should perform fine, even if a bit slower due to their design, but performance sensitive applications will need to be tweaked a bit to run effectively. The Apple Silicon uses the ARM instruction set, which is RISC, meaning that it runs fixed-length simple (Reduced Instruction Set Computing) instructions. Program instructions that take only one instruction on an Intel CPU, will have to be broken down into multiple instructions on RISC, running more instructions of course takes more time. There are things that can be done to mitigate this (pipelining, increasing the number of instructions that can be executed per clock, etc..), but it has to be done. That is why Apple made the dev kits available so early, and also why they announced that your iOS apps can run, because I imagine that for a little while at least, these apps will perform better than the initial set of recompiled apps. Good luck!

Rich S.

I’m sorry, but what you are mixing a bunch of basic facts with a load of random hogwash. Yes, ARM is a load/store ISA, so it sometimes needs two instructions to do what x86 can do with one, but then again ARM has plenty of instructions that don’t exist in x86, not to mention that it has twice as many registers and generally needs less stack juggling. The “running more instruction takes more time” is a plainly wrong since both ARM and x86 CPUs will translate the instructions into RISC-like microcode which then get reordered on the fly. It’s just that x86 can sometimes encode a sequence of such micro-ops more compactly, but then again it used variable length instructions, which are more costly to decode.

Apple CPUs have been analyzed in detail, they are very wide superscalar devices with large caches, perfectly capable of executing any kind of code (save for HPC stuff where newest Intel has an advantage with 512bit per clock AVX - Apple mobile can currently only do 378bit per clock). No, you don’t need to tweak your code to take advantage of it - the CPU will execute it out of order automatically to ensure that the bs kind is efficiently utilized. Just like with any other high-performance superscalar CPU.

And yes, all it takes is a recompile, unless your program has latent bugs (that might not become apparent when executed on a x86-64 CPU) or you are using CPU-specific features (which you will need to rewrite). Obviously you’ll need to test your apps for the new architecture, that goes without saying- same thing as updating your app to a new OS.
 
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5-7% faster than Skylake? Or than Comet Lake in particular? Either way, that's pretty bad.

Same thing. When I say Skylake, I am including all of its optimizations, up to Comet Lake. After all, they are pretty much identical when it comes to the architecture, the differences are mainly process improvements and some little tweaks here and there. The original Skylake obviously was not capable of reaching 5.0 GHz, but 5 years worth of optimizations got Intel there (what they call Comet Lake).
 
Yeah but these are for 13” MBP and the 13” MBP is rumored to be updated either late this year or early next year using Apple Silicon. It will be among the early ASi Macs so no sense in putting Intel in a few months before that, especially since they were just recently updated already.
That’s possible but it’s all rumor, we have no way to know for sure when the product lines will transition. The rumors look more likely that a 12 inch MacBook will be released with Apple Silicon leaving the current 13 inch Pro on Intel for the time being.
 
Apple has this game mapped out 5 years in the future or more. Nobody in Cupertino is batting an eyelash.
 
The announcement is always fine and dandy, but when will these actually ship? And in volume? That’s the problem with Intel and that really annoyed Apple.
 
I see, and how is anyone not familiar with the lakes near Washington suppose to know this?

A quick look via an Internet search engine or Wikipedia would provide an answer.

Also, even if one is not familiar with the specific locales, if they are familiar with Intel's historical naming conventions, they would know Intel uses Pacific Northwest geography for this purpose so it would be safe to presume that Tiger Lake was a lake in the Pacific Northwest.
 
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I got to hand it to Intel's marketing department... talk about thick skin lol.. "the best.." lol. New Netflix comedy special?
 
Ok. Now they are trying. Too late.
Hm, don't think so. If the benchmark results they showed today are at least somewhat representative, this CPU will likely crush AMD's mobile CPU offerings when it comes to single-threaded performance, which is what counts most on laptops. On top of that the GPU seems to be great. I think this thing will sell like hotcakes and it'll help them defend their 80% market share in the biggest slice of the client computing segment.
 
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How is it going to be possible for a SOC that draws 15w to be equalling a GPU that draws 350w of power.
Apple said they are developing a family of SoC's for the Mac. Why do you assume they're going to draw only 15w?
 
Meanwhile, AMD had moved to 4.5GHz clock 7nm process year ago and going to have embedded 7nm Vega series GPU.

Shame on you, Intel.
 
Why do some of you talk about the future with such confident certainty? Some of you are acting like you're a time traveler from 2030 who's telling us events that have already happened.
Wait, who said something? We’re not supposed to talk about that. Dang it, now we’re going to have to start the timeline all over again.
 
Yes.



No. Apple has a long history of letting Mac's "go stagnant". Look at the Mac Mini or the Mac Pro over the last decade.

Never once for Macbook Pro line up. It "stagnant" only for mac mini / mac pro product due to much lower margin.
 
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