I'm not a chip designer, frankly I'm an automation tech, but you could save a lot of trouble here if you could just print out the formula for power draw in CMOS electronics. I can't remember it off the top of my head.
In any event beyound static power draw or leakage power in CMOS logic varies with clock rate. Apparently many here don't know the difference between a GHz and a volt.
As to DYNAMIC voltage adjustments to a running CPU I do not believe that is happening with i86 class processors but I could be wrong as it has been a very long time since I cared about such things. That being said it wouldn't be impossible as modern CPUs can or do control the voltage regulator. From a technical standpoint I suspect that dynamic voltage adjustment would be a big problem for this class of CPU and frankly dynamic gating and shutting off non functional blocks would be much bigger gains. Things do change so I could be wrong but frankly I'd rather see documentation instead of random claims from people that mix GHz and volts.
As to those claiming that 4 CPUs running at a 1/4 of the clock rate of a single core draw less power yes that is possible given the same process and CPU design. But there are qualifications here. For one your static power has to be very low otherwise a good portion of your power budget goes to keeping those for cores turned on. Then you have to consider efficiency of execution, if the software in question requires a fast CPU you loose running on a slow core. In other words 4 CPUs running at 1/4 the clock rate of a single core does not always equal single core performance. I see Intels Turbo Boost as recognizing this. In the end a multi core chip is likely to use more power than a single core chip to complete a quantum of single threaded work.
Dave
Power draw = static + dynamic = static + C x VxV x f. (sometimes times "1/2" depending on how you define "f").
Static power draw increases as voltage decreases (because the low voltages can't shut the devices all the way off) and also increases as feature size decreases - particularly gate thickness.
Of course, f is a function of V, though not necessarily a strong function - if V is too low, then the rise and fall times (switching) can increase to the point where they set the frequency. Ordinarily you don't want to be anywhere close to that point, however, because the longer your rise/fall times, the greater the chance of functional failure due to noise induced during the switching.