Oh my gosh I just lost it when I read this one:
....oh man, I should drag out that old post I made a few months back last time someone asked this question, where I made up a lengthy explanation that was completely wrong and deliberately misused big words and contradicted myself repeatedly and wrote it in such an official way that everyone believed me.
A quote from Air, a PCSX2 Programmer:
Because the PS2 is a lot fancier than you think it is.
That's the short answer. The long answer requires an in-depth technical understanding of micro-architecture and parallel processing. I'll do it in small steps:
Step 1: The 300mhz Emotion Engine is superscalar. It runs 2 instructions at a time, and rarely ever stalls both pipelines. This makes it unique from previous MIPS cpus such as the R4000 or R3000, which only run one instruction at a time, and stall quite often on loads, stores, and other instructions. So by being 300mhz it's actually closer to 600mhz in terms of instruction throughput, and closer to like 800mhz if you wanted to compare it to an R4000, and would be something equivalent to a 1.2ghz R3000.
Step 2: The Emotion Engine has its own built in set of MMI instructions which are special to it. No other MIPS cpu has them, and they are rather exceptionally complicated to implement. Most of the MMI instructions run in a single cycle (and thus a throughput of two per EE clock cycle!), but require between 3 and 6 ix86-SSE instructions to emulate (some instructions require over a dozen SSEs to perform!).
Step 3: The VU0 and VU1 are built the same way. They are superscalar and capable of running two instructions on every clock cycle. Both the VU0 and VU1 are 150mhz. 150x2, and then times 2 again since both chips run in parallel: That's another 600mhz of dedicated SIMD instruction processing, in addition to the EE's.
Step 4: The EE has 32 128-bit registers, and each VU has 32 128-bit registers and 32 32-bit registers. That's a grand total of 96 128-bit registers and 64 32-bit registers. Your fancy ix86 cpu has like 16 128-bit registers and 16 64-bit registers.
Step 5: And none of this even begins to address the inherent complexities of the PS2's memory bus and DMA controller, which require quite a lot of emulated management due to the number of concurrent processors all trying to share the bus at the same time, and still stay in sync.