thenewperson
macrumors 65816
I know, was just mentioning the others in an “if Apple hasn’t done this for them…” sense. Like I said in my comment, it’d be nice for the base to go up to 64GB.
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M4+ Chip Generation - Speculation Megathread [MERGED]
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I know, was just mentioning the others in an “if Apple hasn’t done this for them…” sense. Like I said in my comment, it’d be nice for the base to go up to 64GB.
At present Apple is charging about $400/16GB for adding memory. Even if went to 32GB to 48GB that would increase the price of the device $400. The basic Mini now with only 32GB is $1,299. Another $1,699. Put a decent drive (1TB ) and at $1,700 ... for a mini.
LPDDR6 doesn't appear to be bring any inherent baseline density increases. SK Hynix has a 16Gb
"... it has successfully developed a 16Gb LPDDR6 ..."
SK hynix Develops 1c LPDDR6, 6th-Generation 10nm-Class DRAM | SK hynix Newsroom
News Highlights SK hynix announced Mar. 10 that it has successfully developed a 16Gb LPDDR61 DRAM based on the sixth-generation 10nm-class (1c) process technology. 1LPDDR (Low Power Double Data Rate): A DRAM standard for mobile devices like smartphones and tablets, featuring low-voltage...
news.skhynix.com
to start Micron seems intent on 'overclocking' LPDDR5 further to start ( if Apple goes that route). They have bigger capacity dies but those also won't be lacking in customers either.
If the smallest sized RAM die was going up from all players then the Mini/MBA would bump in capacity. But if the primary focus is on 'faster' chips then the move to '6' isn't going to be some inherent density increases.
"3Dx3D" means 3D on 3D. The SoIC assembly is treated like any other 'chip' in Info/CoWos. That doesnt' mean the SoIC isn't SoIC.
This is covered in the same page I linked in before (post 2,290 back a page) with the examples of 'horizontal' SoIC. ( I'll try to use quotes around horizontal in the SoIC context because I suspect some are inferring that isn't 3D when in reality it is. )
" TSMC-SoIC® technology service integrates both homogeneous and heterogeneous chiplets into a single SoC-like chip. With a smaller footprint and thinner profile, this chip can be holistically integrated into CoWoS® and InFO. From the outside, the integrated chip looks like an ordinary SoC. But on the inside, it is embedded with heterogeneously integrated functionalities. ..."
https://3dfabric.tsmc.com/english/dedicatedFoundry/technology/SoIC.htm#SoIC_CoW
and comes with the diagram of
The SoIC components are also thinned out so it it is just as chip-tick are the other SoCs so can layer another level of '3D' with much less dense pad/bump/connectors on top of that. So the get treated just the same as 'old' thick IC.
That has little to do with the diagram I put together or what 'is' or 'is not' SoIC.
On that same page above this section:
" ...
Exceptional Heterogeneous integration (HI)
Integrating known good dies (KGDs) with different chip sizes, functionalities and wafer node technologies.
(a) System-on-Chip (SoC) before chip partition; (b), (c), (d) Variant TSMC-SoIC® partitioned chiplets and re-integration schemes ..."
(c) is a named varaint of TSMC-SoIC . That is the 'horizontoal' only placement. It is still 3D in reality. The package marketing folk might label that as a 2.5D, but that is mostly hooey just like calling the chips 2nm 1nm when actual features are not that small. 2.5D stuff is 3 dimensions. There are vertically stacked layers. Essentially '2.5' comes from wanting to label one of those layers are "uninteresting enough to talk about". That is 'just' an interposer implemented as a silicon chip that isn't sexy enough to talk about so subtract 0.5 from the dimension number. It still has 3 dimensions in construction. [ historically the interposers had a variant of implementation material there were not an IC so 0.5 is trying also to shade that from being a '3D chip' set up, but even if there is a chip in there that isn't interest... some -0.5 deduction. ]
In the following diagrams, if all of the dies are all connected with exact same 'SoIC' bump sizes and via wires they all should fall under being SoIC implementations.
The second and third is really how the 'hoizontal placement could be approached. The third probably would need some scaffolding to hold it together at interium steps of the final assembly, but that is packaging around the packaging.
The M5 Pro/Max does not look like the first one. If viewed the second from below or third from above is what the die shots of what the M5 Pro I linked in look like. Respectively SoIC 1 and 3 in those diagrams could be the 'uninteresting' interposer die. So in the eyes of some not worthy of the '3D' label , but that isn't reality. All three of those diagrams are 2 dies high. All of them had a z-axis die height count of two. Since there is are x and y axis that cannot see from this view but exist in reality, you have x , y and z points in this package. That is 3 dimensions.
In my diagrams in the previous post in this chain the 'blue' marking are really markings of connections to the die down below. That is where the vias and bumps are. The puzzle aspect of how these dies fit together is far more in the x-y plane than looking frontal at the z plane (like these ). The dies merely have to on top of each other in same way to get the 3D part worked out. That isn't harder part here (SoIC vias and bumps directly address that).
If Apple's individia dies primarily use mesh routing to more data from one side of the die to the other then it may be useful to put a mesh routing on the "interposer' die also to start the directional routing as the data moves to the other side. For very small interposer with hyper short distances that could not necessary ( e.g., on the Pro/Max set up). But for the 4 way interchange the connection points are going to move farther apart. My "box' solution gets rid of one of those bigger directions, but there is no way to get rid of both. That IC interposer there is going to have to do something somewhat 'interesting'.
Info-LSI which was used the previous Ultras was basically the same thing The SI interposer die is bonded to the Max dies with bigger bumps and bigger vertical 'wires' but the general approach is exactly the same.
SoIC just uses even smaller bump sizes on the silicon IC (or 'LSI') dies involved. The dramatic decrease gets a new name and the degree of interposer activeness and total eclipsing overlap goes up. However, for the 'horizontal' implementation variant there isn't a major structural change. [ the tools and steps in building probably need a huge upgrade , but same basic structure. ]
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Vincent Hanna
Suspended
These people can buy Mn Pro chips. Apple has no motivation to let base M chip sales encroach on Mn Pro and Mn Max sales.
As long as there is a substantive limitations on memory supply it is more so Apple doesn't want to engage in a "Rob Peter to pay Paul" context where take higher density RAM away from Pro/Max and assign it to the base/plain Mn chip. They would be leaving Pro customers without supply to somewhat 'oversupply' the Mn series customers.
If there was a gigantic glut of memory that perhaps the base chip could help work down that excess. However, for the next several years that is fantasy land. No long , sustained periods of glut coming for anywhere in the intermediate future.