I remember Intel being one of the original companies that was onboard to use N3B, but I thought I read that Intel had backed off due to cost/compatibility issues*. Maybe they just scaled back at first? But I have read many reports that N3B was more expensive and complicated due to the half a dozen or so more layers. And that Apple had reserved most, if not all, initial production?
N3B is more expensive even before get to yield; the wafers just cost more. Follow on N3-family probably will cost more also. Even N3E costs substantively move than N5/N4 though. N3B was just even more than that.
Intel hugely delayed their wafer usage allocation. There was some notion that perhaps that was to wait for N3E, but it turns out it was mainly Intel being late because chasing 'everything at the same time' and was designing Arrow lake for multiple fabs at the same time. ( and also skittish on the Lunar Lake approach with DRAM soldered onto the subassembly. )
" ... TrendForce yesterday issued a report claiming that Intel had decided to postpone the start of Meteor Lake's GPU tile production on TSMC's N3 node from late 2022 to 'late 2023,' which allegedly caused TSMC to revisit its N3 capacity investment plans. ..."
Cannot comment on specific customers, but there is nothing to comment.
www.tomshardware.com
There are some issues here because the Meteor Lake's GPU tile was done on TSMC N5. Was that due to hardware quirks in GPU hardware that needed fixing or because N3 wasn't really going to make it in volume by Q4 2022. Or some combo of both.
There are other rumors that Intel cut their wafers way back when shifted plans to split production on Intel 20A and N3B for the Arrow Lake line up. TSMC cut their 'volume' discount , but Gelsinger/Intel thought get more milage out of show viability of 20A (to attract fab customers? ). Turns out didn't really work. Five nodes in four years really was "a Bridge too far".
N3E also has "more layers and complication" than N5/N4. N3B just somewhat stretched about to limit of abilities. Because it takes longer to make , the iterative Quality Assurance improvement process took longer. Then TSMC had customers moving slower ( not moving volume. Missed iPhone volume window. ). Intel dropping out of early production, just made the improvement cycle even longer.
However, that was largely blown out of proportion by the rumors mill as N3B was incurably bad and never would yield in decent volumes.
I think Apple somewhat defacto reserved the initial production largely because everyone else wasn't buying. Not that it wasn't for sale.
Well if it wasn’t production issues, then I guess the only other thing I can think for the M3 Ultra “delay” was they wanted to upgrade the Thunderbolt controllers. Just seems weird that they waited until after almost everything moved off N3B, to start fab’ing these SoCs. That and that they’re only producing the two variants; base and Ultra.
I don't think they wanted to 'upgrade' the Thunderbolt controllers as much as match them. If fully committed to using the M4 Max on the lower half of the Studio line up. How are they going to 'miss' TBv5 on the upper half?
Thunderbolt is also has substantive portions that are 'I/O' (off die) oriented. N3-whatever doesn't bring much shrinkage there. If not pushing the M4's TBv5 very hard on the fringe of N3 tech it shouldn't be too hard to place in on both N3B and N3E if don't sure either one for max density.
If they have to make a M3 Max+ die anyway to put the UltraFusion connector on the larger die, they need a new die mask anyway. So adding in TBv5 would not a huge incremental effort.
*Now that I think about it, it can take years to design these chips, so the option of just throwing the design out is usually not feasible and doesn’t really make sense. Especially since the N3B is completely incompatible with the rest of the ”3nm” nodes.
N3E SRAM (cache ) density is the same as N5/N4. "completely incompatible" is a bit of an overstatment. I/O circuits also really didn't go anywhere radically new (size and density) either . The "incompatible" is far more grounded in the densest logic circuit options between N3E and N3B. If they don't aim at those , then they don't 'hit' those incompatibilities quite as hard.
Where Apple is primarily using N3 logic density gains ( the CPU cores , GPU cores , NPU cores ) really are not changing between the laptop M3 Max and the M3 Max+ . Memory subsystem isn't changing much either ( using denser RAM dies is off the primary M-series die.).