What craziness is this?
Doing more than one instruction at a time per core is NOT a "CISC"-like thing. Every RISC processor can do that (other than some toys in labs, or what not). Hell, in 1997 I designed hardware to enable that for UltraSparc V.
The difference between RISC and CISC has nothing to do with that.
The main differences:
1) CISC instructions are typically variable length, making decoding more difficult
2) CISC typically allows ALU instructions to directly modify or read from RAM, and has more complicated addressing modes, making instruction decode and memory access contention more difficult
3) CISC typically uses microcode to break down these complicated instructions into simpler RISC-like instructions. That requires a sequencer, Microcode rom, etc. The trade-off is: let the compiler figure out how to efficiently break a problem down, or let the CPU try and do it on-the-fly.
4) Most RISC instructions take the same amount of time. This simplifies pipelining, resulting in fewer pipeline bubbles (in theory)
5) RISC typically has more registers. This reduces the need to hit slow memory, but at the potential cost of higher penalties for context switching.