If they didn't release the announced updates today. Does that mean there won't be one for some time.?
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Evangelion said:
To be fair, they can have have the same bandwidth, under the premesis that it's a single G5 system (iMac) vs. a single Opteron/A64. The AMD jobs manages to reach higher sustained bandwidth numbers though.
(And yes, I allso think that the IMC solution is superior)
Sorry to say this, but no it doesn't. The Opteron has got a 64kB L1 I and a 64 kB L1 D cache, the 970 has got a 64kB I and a 32kB D cache.
</nitpick>
Carry on now.
SaleenS351 said:
I think every day is possible! like allready some people said: There is this smaal special event at the end of the day coming up... so who knows?
Eric_Z said:
In single-CPU-systems, AMD-systems do have more bandwidth than G5-systems do. While the FSB on the G5 can be faster (starting from 2GHz G5, the FSB is as fast as on A64/Opteron, and it gets faster as the CPU gets faster), AMD systems have integrated mem-controller, whic seriously increases effective bandwidth. On the G5, memory-access goes through the FSB, and that eats ALOT of bandwidth. On the AMD-system, the CPU has a dedicated channel to the RAM, and the FSB is dedicated to other devices (AGP, PCI, IDE etc.).
If you want to calulate the available bandwidth on the systems, on the AMD-system you should add the mem-bandwidth to the FSB-bandwidth in order to get the total bandwidth available to the CPU. On the G5 there is no dedicated mem-channel, so the FSB is the only thing there is.
For example:
1x 2.0 GHz G5: 1Ghz bus. That gives it 8GB/sec of bus-bandwidth. And the RAM has 6.4GB/sec of available bandwidth. So accessing the RAM leaves just 1.6GB of bandwidth to other uses.
2x 2.5Ghz G5: 2x 1.25 GHz bus (one for each CPU). each CPU has 10GB/sec of bandwidth, for a total of 20GB/sec. RAM still has bandwidth of 6.4GB/sec. If both CPU's access the RAM in the same time, each CPU can get only 3.2GB/sec. If only one CPU accesses the RAM, it eats 64% of the available FSB-bandwidth.
1x Athlon64: 1Ghz bus + dedicated 128bit DDR-mem-channel. The FSB has 8GB of bandwidth available, and that bandwidth is dedicated to USB, PCI, AGP, IDE and the like. Memory has 6.4GB of dedicated bandwidth available, for a total of 14.4GB/sec of bandwidth.
2x Opterons: 2x 1Ghz bus (one for each CPU) + dedicated 128bit mem-channels + 1Ghz bus to the other CPU. Each CPU is connected to the rest of the system through 8GB/sec bus. And they can access their local RAM through 6.4GB/sec bus. But they can also access the RAM connected to the other CPU. So each CPU has 8GB/sec of "system bus" at it's disposal + 12.8GB/sec of mem-bandwidth available. So each CPU has 20.8GB/sec of bandwidth. Adding the second CPU, we get 28.8GB/sec of total bandwidth (the amount of mem-bandwidth is not increased since it has already been calculated in to the first number).
In summary:
1x 2GHz G5: 8GB/sec of bandwidth
2x 2.5GHz G5: 20GB/sec of bandwidth
1x A64: 14.4GB/sec of bandwidth
2x Opteron: 28.8GB/sec of bandwidth
4x Opteron: 57.6GB/sec of bandwidth
8x Opteron: 115.2GB/sec of bandwidth
Hope I got the math right
.With the Opteron, the latency does go up a bit as the number of CPU's increase. But the latencies are still very low when compared to accessing the RAM through the northbridge. Of course, there are system where some CPU's have no RAM of their own. In those cases, the mem-bandwidth does not go up. But if each CPU has a RAM-bank available, the amount of bandwidth increases as number of CPU's go up.
Well so it is. My mistake
.
This just screams for an integrated memory controller in the G5 Macs, I think. Remember that Macs aren't NUMA-based (unlike the Opteron), and thus won't benefit from the division of memory into banks for each CPU to increase total bandwidth. To me, though, that's actually a disadvantage - you're artificially limiting each CPU to a fraction of the RAM available: the numerator of this fraction will always be 1; the denominator will be the number of CPUs in the system.Evangelion said:In single-CPU-systems, AMD-systems do have more bandwidth than G5-systems do. While the FSB on the G5 can be faster (starting from 2GHz G5, the FSB is as fast as on A64/Opteron, and it gets faster as the CPU gets faster), AMD systems have integrated mem-controller, whic seriously increases effective bandwidth. On the G5, memory-access goes through the FSB, and that eats ALOT of bandwidth. On the AMD-system, the CPU has a dedicated channel to the RAM, and the FSB is dedicated to other devices (AGP, PCI, IDE etc.).
If you want to calulate the available bandwidth on the systems, on the AMD-system you should add the mem-bandwidth to the FSB-bandwidth in order to get the total bandwidth available to the CPU. On the G5 there is no dedicated mem-channel, so the FSB is the only thing there is.
For example:
1x 2.0 GHz G5: 1Ghz bus. That gives it 8GB/sec of bus-bandwidth. And the RAM has 6.4GB/sec of available bandwidth. So accessing the RAM leaves just 1.6GB of bandwidth to other uses.
2x 2.5Ghz G5: 2x 1.25 GHz bus (one for each CPU). each CPU has 10GB/sec of bandwidth, for a total of 20GB/sec. RAM still has bandwidth of 6.4GB/sec. If both CPU's access the RAM in the same time, each CPU can get only 3.2GB/sec. If only one CPU accesses the RAM, it eats 64% of the available FSB-bandwidth.
1x Athlon64: 1Ghz bus + dedicated 128bit DDR-mem-channel. The FSB has 8GB of bandwidth available, and that bandwidth is dedicated to USB, PCI, AGP, IDE and the like. Memory has 6.4GB of dedicated bandwidth available, for a total of 14.4GB/sec of bandwidth.
2x Opterons: 2x 1Ghz bus (one for each CPU) + dedicated 128bit mem-channels + 1Ghz bus to the other CPU. Each CPU is connected to the rest of the system through 8GB/sec bus. And they can access their local RAM through 6.4GB/sec bus. But they can also access the RAM connected to the other CPU. So each CPU has 8GB/sec of "system bus" at it's disposal + 12.8GB/sec of mem-bandwidth available. So each CPU has 20.8GB/sec of bandwidth. Adding the second CPU, we get 28.8GB/sec of total bandwidth (the amount of mem-bandwidth is not increased since it has already been calculated in to the first number).
In summary:
1x 2GHz G5: 8GB/sec of bandwidth
2x 2.5GHz G5: 20GB/sec of bandwidth
1x A64: 14.4GB/sec of bandwidth
2x Opteron: 28.8GB/sec of bandwidth
4x Opteron: 57.6GB/sec of bandwidth
8x Opteron: 115.2GB/sec of bandwidth
Hope I got the math right
With the Opteron, the latency does go up a bit as the number of CPU's increase. But the latencies are still very low when compared to accessing the RAM through the northbridge. Of course, there are system where some CPU's have no RAM of their own. In those cases, the mem-bandwidth does not go up. But if each CPU has a RAM-bank available, the amount of bandwidth increases as number of CPU's go up.
Well so it is. My mistake
wrldwzrd89 said:
If G5 moved to integrated mem-controller, the system would become more or less NUMA by default. Of course the OS would have to be made NUMA-aware as well to take real advantage of it.
It's not really a disadvantage. Sure, each CPU has a "local" and "remote" RAM. But each CPU can access the entire RAM as well, the latency just goes up a bit. So the CPU's are not limited, since they can access the other RAM just fine as well. As far as the entire system is concerned, the total RAM is what matters, even though it would be split between two CPU's. So 1GB of RAM is 1GB of ram, and not 2x512MB for example. The OS could have some extra IQ in such way that processes meant for certain CPU's would be located in it's local RAM. And I think all NUMA-aware OS'es do that already. So for the apps and users, the whole process is completely transparent. Only thing they see is that their system has lots and lots of mem-bandwidth.
But, if you want to mimic the behavior of Intel of PPC-based system on an multiprocessor-Opteron system, you could just put all the RAM in to one memory-bank. In that case, all the RAM would be local to one of the CPU's and remote for the other (you could say that on systems where the RAM-access goes through the northbridge, all RAM is remote to all CPU's). But that would mean that the mem-bandwidth doesn't increase.
I had no idea that NUMA used a local-remote concept to get around the bank limit problem. That fact alone makes implementing an IMC, and therefore NUMA, more than worthwhile. The issue of operating system-level support still lingers, though - unless Apple killed this one dead in Tiger.Evangelion said:
MacCoaster said:A bit off topic, but Seagate recently released a 100 GB 7200 RPM laptop drive.
well, it was about time already. i installed a 7k60 in july 2003 into a titanium powerbook, and we all know 20 months is forever...
wrldwzrd89 said:
the G5 powermac was born in wwdc2003, updated in wwdc2004 and now rumoured to get a spec-refresh strangely few months before wwdc2005. what doesn't fit in the picture? maybe steve wants to announce something very big that will not ship until september(ish)...?
This better be a hoax done by Apple or the iMac will continue to cannibilize the PM sales. 10 months to squeeze 200-300 MHz per processor!??!?! C'mon Apple. Thats BS. Hopefully they're just telling ThinkSecret this to throw them off their trail.
Hopefully they're just telling ThinkSecret this to throw them off their trail.
Reanimation_LP said:This better be a hoax done by Apple or the iMac will continue to cannibilize the PM sales. 10 months to squeeze 200-300 MHz per processor!??!?! C'mon Apple. Thats BS.
Thats what everyone thought when the specs for the latest Powerbooks came out....and they got even less of a speed bump lol. ThinkSecret are usually pretty accurate so I think these specs are reasonably accurate.
G5 does *not* put memory on HyperTransport (neither does AMD)
The G5 uses the IBM "elastic bus" FSB between CPU and Northbridge (U3/U3H). A 16-bit HyperTransport goes from the Northbridge to the PCI-X Tunnel, then as an 8-bit HT to the Southbridge.
http://developer.apple.com/document...rMacG5/2Architecture/chapter_3_section_2.html
This picture is for the PCI-X 8 memory slot systems. Follow the link to see the diagram for the PCI 4 memory slot systems (no PCI-X tunnel, just the 8-bit HT to the Southbridge, and PCI off the Southbridge).
Evangelion said:
The G5 uses the IBM "elastic bus" FSB between CPU and Northbridge (U3/U3H). A 16-bit HyperTransport goes from the Northbridge to the PCI-X Tunnel, then as an 8-bit HT to the Southbridge.
http://developer.apple.com/document...rMacG5/2Architecture/chapter_3_section_2.html
This picture is for the PCI-X 8 memory slot systems. Follow the link to see the diagram for the PCI 4 memory slot systems (no PCI-X tunnel, just the 8-bit HT to the Southbridge, and PCI off the Southbridge).
Slow CPU advances
You folks need to realize that CPU advancements now are nothing like they were in the 1990s, and that goes across the board including Intel chips. Dual core is most definitely NOT double the speed.
I realized this about middle of last year, looking at what was going on in the CPU world and why my 2 year old Athlon was still doing just fine. A cut and paste from a post I put on a *.chips newsgroup :
"
Fastest CPUs in the Nov/Dec time frame by year :
Nov/ Dec 1998 : K6-2 400 / Pentium 3 400
Nov/Dec 1999 : P3-800 / Athlon 800 (One year)
Nov 20th, 2000 : P4 1.4 / 1.5 Ghz (One year)
Nov 2002 : 3.06 Ghz P4 (Two years)
Nov 2004 : 3.6 Ghz P4 / Athlon64 4000+ (Two years)
LOOK at the numbers, both Mhz *and* architecture.
1998 -> 1999 (ONE year) we had a doubling of CPU Mhz AND a more
advanced architecture release (Athlon).
1999->2000 (ONE year) cpu speed DOUBLED again AND a more advanced
architecture released (P4).
2000->2002 (TWO years) speed DOUBLED.
2002-2004 (TWO years) A new architecture was released (Athlon 64).
Speed went up by 15% on the same architecture P4. If you use AMDs PR
system, the A64 gave us 33%.
"
Look at what happened. We went from doubling speed every year, to doubling every 2 years, to a paltry 15-33% increase over 2 years. Some of the finer points can be argued, like increases in L2 cache. Bottom line though, the main advancements in the last 2-3 years have not come from CPUs but rather GPUs, memory architecture, and bus architecture.
The slow rate of advancement in CPU tech is endemic throughout the industry now - it isn't just Apple. The logic of upgrading every 1-2 years that served in the 1990s just doesn't hold true anymore. Best bet is to buy the best machine you can afford, now, and figure on keeping it for 4 or 5 years. That's the new paradigm.
You folks need to realize that CPU advancements now are nothing like they were in the 1990s, and that goes across the board including Intel chips. Dual core is most definitely NOT double the speed.
I realized this about middle of last year, looking at what was going on in the CPU world and why my 2 year old Athlon was still doing just fine. A cut and paste from a post I put on a *.chips newsgroup :
"
Fastest CPUs in the Nov/Dec time frame by year :
Nov/ Dec 1998 : K6-2 400 / Pentium 3 400
Nov/Dec 1999 : P3-800 / Athlon 800 (One year)
Nov 20th, 2000 : P4 1.4 / 1.5 Ghz (One year)
Nov 2002 : 3.06 Ghz P4 (Two years)
Nov 2004 : 3.6 Ghz P4 / Athlon64 4000+ (Two years)
LOOK at the numbers, both Mhz *and* architecture.
1998 -> 1999 (ONE year) we had a doubling of CPU Mhz AND a more
advanced architecture release (Athlon).
1999->2000 (ONE year) cpu speed DOUBLED again AND a more advanced
architecture released (P4).
2000->2002 (TWO years) speed DOUBLED.
2002-2004 (TWO years) A new architecture was released (Athlon 64).
Speed went up by 15% on the same architecture P4. If you use AMDs PR
system, the A64 gave us 33%.
"
Look at what happened. We went from doubling speed every year, to doubling every 2 years, to a paltry 15-33% increase over 2 years. Some of the finer points can be argued, like increases in L2 cache. Bottom line though, the main advancements in the last 2-3 years have not come from CPUs but rather GPUs, memory architecture, and bus architecture.
The slow rate of advancement in CPU tech is endemic throughout the industry now - it isn't just Apple. The logic of upgrading every 1-2 years that served in the 1990s just doesn't hold true anymore. Best bet is to buy the best machine you can afford, now, and figure on keeping it for 4 or 5 years. That's the new paradigm.
edgarj said:
I remember when the same as said about AGP replacing PCI for graphics. The technical merrits of PCI-e and AGP don't matter. What does matter is that future graphics cards will not be made for AGP. If we don't want our lineup to consist of the GeForce FX 5200, Radeon 9600, and Geforce 6800 for the foreseable future, we need to upgrade.
My guess is that if they don't surprise us at the invite only event today at NAB, they will quietly roll out the PM speed bumps that TS predicted within the next couple of weeks. I'm still holding out that something special will be revealed todayle_coc said:
Now I am glad I didn't wait to buy my Powermac at the Begining of the month!
Granted, this is STILL a rumor, and we have yet to hear anything official from Apple. So there may be hope.. Rumor sites have been known to be wrong.
Granted, this is STILL a rumor, and we have yet to hear anything official from Apple. So there may be hope.. Rumor sites have been known to be wrong.
It's fun making predictions so here are my 2 cents:
Apple will replace existing line with the dual 2.0, 2.3 and 2.7 as predicted by TS while lowering prices accross the line with about $ 500 to keep them competitive against the AMD and Intel dualcores.
At WWDC Paris they will introduce the dualcores adding two new high-end models to the existing line: quad 2.0 and quad 2.3.
Apple will replace existing line with the dual 2.0, 2.3 and 2.7 as predicted by TS while lowering prices accross the line with about $ 500 to keep them competitive against the AMD and Intel dualcores.
At WWDC Paris they will introduce the dualcores adding two new high-end models to the existing line: quad 2.0 and quad 2.3.
products to market
I wish you people knew what it took to bring a product to market. for a complete ground-up design, it can take upwards of 4-5 YEARS to get that design to market. there are a million considerations when designing, testing, characterizing, and qualifying a part for production.
If it's not a ground-up design, cut off a year or two.
this is complicated stuff. Do realize how many states a processor can be in???
2 ^ (number of transistors * 0.8) .
the 80 % factor is for transistors not used in functional mode.
I guess my point is for you to understand playing catch-up is hard. True, some better choices could have been made, and I get a little irritated at that fact, but there's nothing we could do except buy AMD procs and switch to Linux. Do you want to do that?
I wish you people knew what it took to bring a product to market. for a complete ground-up design, it can take upwards of 4-5 YEARS to get that design to market. there are a million considerations when designing, testing, characterizing, and qualifying a part for production.
If it's not a ground-up design, cut off a year or two.
this is complicated stuff. Do realize how many states a processor can be in???
2 ^ (number of transistors * 0.8) .
the 80 % factor is for transistors not used in functional mode.
I guess my point is for you to understand playing catch-up is hard. True, some better choices could have been made, and I get a little irritated at that fact, but there's nothing we could do except buy AMD procs and switch to Linux. Do you want to do that?