Yes, because it makes sense to do so. I am very well aware of the differences. And I don't see from you arguments below, where I was wrong?
That doesn't really change the fact, that the M3 is likely to be 3nm based.
More often than not, you can't do a process change without doing an architecture change. But not sure why you think this is relevant to my post?
Sure--here was my thinking:
You were replying to a poster who was wondering what the advantage was in going from 5 nm to 3 nm. You wrote:
"Smaller electronics in the chips means they use less power and thus produce less heat, or alternatively, Apple can dial up the speed more, when switching from 5nm chips to 3nm chips. It is not going to make them 200% faster, but the jump from M2 to M3 is thus likely significantly larger than the one from M1 to M2."
So in the first sentence you explained, correctly, the primary advantage in going from 5 nm to 3 nm. Then in the 2nd sentence, where you tried to give a sense of the magnitude of the advantage, instead of writing "the jump from 5 nm to 3 nm", you wrote the "the jump from M2 to M3", which gives your audience the misimpression that 5 nm = M2 and 3 nm = M3, when in fact they're two qualitatively different designations.
That is why I said you seemed to be conflating the two.
I would have instead written something like this:
"[Your first sentence, then...] According to TSMC, if you use all of that process improvement for speed, everything else being equal, a chip will have ~10–15% better performance on 3 nm than 5 nm.
But: That's not the only generational improvement you can make.
Separately, you can also improve the chip's performance by improving its "microarchitecture", i.e., its design. That's what the M1/M2/M3 designations mean.
Thus there's three possibilities for the next gen MBP's:
1) Stay with both the same process (5 nm) and the same microarchitecture (M2) as on the current Air and 13" MBP (that wouldn't, of course, stop them from improving the coprocessors, like the neural engine, etc.). That's what we'd expect to see with a fall release.
2) Improve the process to 3 nm, but keep the microarchitecture the same (=> a 3 nm M2).
3) Improve the process to 3 nm, and also upgrade the microarchitecture to M3 (=> a 3 nm M3). Then you'd get the improvement from the microarchitecture on top of the improvement from the process."
And then I might close by saying somethign like:
"You may recall hearing of Intel's "tick-tock" production model. In it, they alternated a process improvement, i.e., a die shrink ('tick') with a microarchitecture improvement ('tock'). This is not Apple's model, but it nevertheless illustatrates how these are two qualitatively different things." [They don't do tick-tock anymore; now, according to Wikipedia, it's more like tick-tock-optimization".]
First there have to be cameras that are equipped with the Uhs III slots and can (want to) write that fast to SD. But in the meantime CFexpress cards took off making space for higher end market.