Of course. By the same token, the frequency of faults for a targeted clock speed for each chip on that wafer determines how to sell the bulk of those wafers whose chips can be certified for up to a certain clock speed.
Historical case in point: when Apple rolled out the PPC 7400 in August 1999, they very quickly ran into a problem: the inability for Motorola (and even IBM) to produce enough 7400 wafers with chips which could reliably be clocked to 500MHz. Few of those chips in any particular wafer, given the manufacturing processes for that moment, could be clocked to 500MHz, and demand would completely outstrip supply.
So Apple, in October that year, downclocked their entire, brand-new line of Power Mac G4s, so that the fastest clock speed one could order was a 450MHz CPU. Many of those chips couldn’t be certified at 500MHz, but could at 450MHz. (Of course, Apple kept all G4 prices the same, which infuriated purchasers who’d been waiting for their G4 tower to arrive, only to know that what would arrive would be 50 MHz slower than what was ordered.)
So to look back on what happened in 1999, Apple — atop all the other logistical issues with delivering a 3.0 GHz PPC 970 product in 2004 — probably kept memory of that not-so-distant issue in mind (it had only been five years) when realizing how to deliver a G5 product clocked at 3.0GHz, successfully, was never going to happen, given near- and mid-term technological and logistical constraints.
These constraints included, of course, the paucity of chips IBM could manufacture which could, feasibly, be certified for 3.0 GHz — even minding the amount of power and active cooling needed to accommodate all that generated heat. It just wasn’t to be, and as far as POWER4-based CPUs go, it still isn’t.