Originally posted by barkmonster
The XServe uses ATA/100 and a 133MHz FSB.
The thing puzzles me is the explaination of RDRAM (or at least the 400Mhz bus) on the intel site :
P4 1.4 - 2.0Ghz info
That's the old version of the P4 with the 256K L2, the new one's running off the same 133Mhz system clock as the entry level G4 but they've quad pumped it to 533Mhz and doubled the L2 cache size.
I think seeing as we've got 2.7Gb/s of bandwidth to share with our PCI cards, AGP graphics card, ethernet, USB, firewire and airport, not to mention the hard drive controllers are both independent of cpu. We should see some improvement over the old motherboard purely because the system controller seperates the cpu's bandwidth from the components.
I'd love to see how these macs perform in Protools LE!!!
All that bandwidth for the hard drives and pci slots has got to have quite an impact on performance.
The difference between Intel, AMD, and Apple is this:
Intel: 100 mhz QDR (transfers data 4 times per clock cycle, making it an effective 400 mhz clock)
AMD: 133 mhz DDR (transfers data 2 times per clock cycle, making it an effective 266 mhz clock)
Apple: 166 mhz SDR (only transfers data once per clock cycle)
Without an architecture change, you can't make a processor that uses a SDR bus go to a DDR bus. You could make it a 333 mhz SDR bus, but it's highly doubtful that the processor would be able to handle that.
Now, the new P4's do use a 133 QDR bus, however, their own chipset still only has a memory bus of 100 mhz QDR, which does still help, but not as much as it could. Remember, even though you have 1.3 GB/s to give to your I/O devices, every I/O device still uses the CPU quite a bit, and generates a lot of traffic on that FSB. Additionally SMP systems generate a lot of traffic on the FSB communicating to each other, and so you end up with only 900 megs of bandwidth left over.
There is no such thing as an I/O device that is independent of a CPU. It will use the CPU in some way, at the bare minimum raising an interrupt everytime data is transferred. You can offload some of the processing, but it's all but impossible to offload everything.