Originally posted by Tim Flynn
The relationship is roughly linear (disregarding leakage).
BUT, at lower speeds you can reduce the voltage, and that's a square law thing, and get your best power reduction.
But the laws of physics tend to get in the way 🙁
To give the same answer with more words...
Yes, the relationship to clock frequency is pretty much linear with everything else held constant:
P=(.5*f*C*V^2)+Pq
(sorry, someone asked for a techie answer...)
P=power
f=clock frequency
C=capacitance, both transistor gate capacitance and routing parasitics. More transistors means higher C. Smaller process or better dielectric means lower C for transistors but typically higher C for routing.
V=operating voltage, smaller process typically allows lower voltage operation. Lower clock speeds allow lower voltage operation.
Pq=static power (clock stopped). This is mostly leakage, and goes up appreciably at very small processes. At 90nm, up to half the power can be static power.
So, if you're doing everything you can to cut power you'd reduce both the clock and the voltage for a non-linear power reduction, bearing in mind that voltage can only be reduced slightly.
As an example of the other factors, Apple Insider quotes: "According to preliminary tests, a 2.5GHz Power PC 970 G5 processor based on the 130nm process consumes 96 watts, while 2.5GHz G5 built around the 90nm process pulls a more manageable 62 watts."
Due only to the process shrink (presumably) the power will likely have seen a reduction in C and V, with an increase in Pq giving a net 30% total reduction at the same clock speed.
Trying to answer the original question is complicated by the fact that folks here can't agree on the power of the
current G5...
🙂