AidenShaw
macrumors P6
jiggie2g said:The woodcrest 1333 chipset is not truely 1333. it's a dual 667. the 2 cpu's, which is what woodcrest is meant for, will both have their own 667 bus, so no sharing, but not high speed either. it's that way for reliability
The Intel 5000 chipset (for Xeon 5100 CPUs) front side bus is a pair of 1066 MT/s or a pair of 1333 MT/s, not two at 667 MT/s.
If the bus is double pumped, the frequency of the bus clock is half the frequency of the data. If quad pumped, the bus clock is 1/4 of the data frequency. Data frequency is almost always used in the spec sheets, not the bus clock frequency. For the Intel 5000, the FSB clock is 266 MHz (1066 MT/s) or 333 MHz (1333 MT/s) - the multiplier is 4, making it a quad-pumped bus.
http://download.intel.com/design/chipsets/datashts/31307101.pdf
The term DIB means Dual Independent Bus, referring to a separate FSB per socket.Page 345 said:The MCH supports 1066 MHz FSB which is a quad-pumped bus running off a 266 MHz system clock, and a point to point DIB processor system bus interface. Each processor FSB supports peak address generation rates of 533 Million Addresses/second.
Both FSB data buses are quad pumped 64-bits which allows peak bandwidths of 8.5 GB/s (1066 MT/s). The MCH supports 36-bit host addressing, decoding up to 64 GB of the processor’s memory address space.
Each socket has its own FSB to the Northbridge, similar to the structure of the G5.
Figure 1.1 on page 23 from: http://download.intel.com/design/chipsets/datashts/31307101.pdf