Yes. There is only one pool of RAM to use, so the CPU and GPU share it (this is true of all mobile phones). It was only with A7 and then A8 that the GPU got access to the L3 cache, though we have no idea how that memory management occurs.
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What to expect from the iPhone 6S, Apple's A9, and beyond
- Thread starter chrmjenkins
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Yes. There is only one pool of RAM to use, so the CPU and GPU share it (this is true of all mobile phones). It was only with A7 and then A8 that the GPU got access to the L3 cache, though we have no idea how that memory management occurs.
Lol! Just trying to help out in case your head exploded while reading all of that info. I know mine nearly did. It was quite the education!
Lots of questions to answer from today
- Is A9X on a FinFET process? They only mentioned new transistor type for A9.
- Core count for both CPU/GPU and any cache size changes. The claimed speedup for both likely means combination of clock and arch changes for CPU. For GPU, likely 7XT Rogue with cluster growth. Still considering 8MB L3 a possibility.
- A9 was essentially confirmed as FinFET. Is is Samsung, TSMC, or both?
- A9 also had very large CPU and GPU performance jumps. Same question as for A9X.
- Lack of memory bandwidth claims for A9 means it's likely closer to A8 solution than A9X is close to A8X's solution.
- For both, question of 2GB RAM or some other number.
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We'll have to wait until Chipworks rips open the iPads and iPhones for the A9(X). As for the raw horsepower: Geekbench scores will tell us exactly what's on the A9 and it's bigger A9X brother.
Can turn this double post into something useful. Apple mentioned 2x2 AC WiFi, which is supported by their 866 Mbps speed claim. That explains the second RF cable from the top of the device to the bottom.
edit: And 7 series GPUs seem confirmed: https://developer.apple.com/library..._ref/c/econst/MTLFeatureSet_iOS_GPUFamily3_v1
credit to https://twitter.com/CommData/status/641712581300879360
edit: And 7 series GPUs seem confirmed: https://developer.apple.com/library..._ref/c/econst/MTLFeatureSet_iOS_GPUFamily3_v1
credit to https://twitter.com/CommData/status/641712581300879360
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I thought LPDDR4 doubled the bandwidth over LPDDR3? Perhaps the A9X is using a 192-bit bus?
Apple showed most of the A9 die during the keynote (or it was a mockup).
My guesses as to the components are as follows:
- Bottom right: 2 CPU cores + L2 cache
- Middle: 2 SRAM blocks
- Top center to top right: 6 GPU cores arranged in three groups.
I thought LPDDR4 doubled the bandwidth over LPDDR3? Perhaps the A9X is using a 192-bit bus?
Apple showed most of the A9 die during the keynote (or it was a mockup).
My guesses as to the components are as follows:
- Bottom right: 2 CPU cores + L2 cache
- Middle: 2 SRAM blocks
- Top center to top right: 6 GPU cores arranged in three groups.
You're right, it is twice as fast. The problem is my source used MHz interchangeably with MT/s and I never fixed it all this time. I'm going to update the tables. I agree about the picture, too.
Since the thrust of your work has been detailed analysis of the A series chips leading up to speculation regarding the latest generation (now A9/A9X), yesterday's presentation threw in something else as well. The M8 has now come into your field of view since it is integrated into the A9 now. Lots and lots of questions on that I think in terms of what resources are shared, separate, added and optimised for low power applications, etc.
Also, I'll be interested to see how always-on Siri affects the silicon design. Listening constantly to audio in order to pattern-match the activation phrase isn't an entirely non-trivial computational activity. How is this being done efficiently? Is this one of the reasons for moving the M chip onto the main SoC, so that it can have a bit more resource to do this activity?
Next year will be interesting too. Might you one day also be dissecting a C10 chip ("C" for communications)? Apple have hired quite a few 3G/LTE/etc chip designers and speculation has been rife that it might be building some of it's own stuff here too (as you alluded to in your second post). One of my thoughts on that is that I assume there are quite a lot of unseen very low power CPU cores hidden in all these LTE, WiFi etc chips and a nice efficiency increase from a unified comms chip could be to aggregate that housekeeping CPU load into a single low power computing resource (one or two very low power CPU cores) and hence reduce the core count. In my musings it would have then made sense to shift the M8/<whatever> computing load to that low power compute resource to further reduce core count.
Basically, I'd be really interested to get a closer look at what's happening with the M8/M9 developments. Also, what do you (crmjenkins) think is the overall core count in an iPhone to include other very low power cores lurking in the various radio and other chips?
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This is the only reason I would upgrade, everything else is icing on the top, but if the performance issues aren't resolved (my 6+ is a crash/reloading/respring nightmare) then I'm just gonna fresh install iOS 9 on my 6+ and wait for the 7. I don't give an eff about 3D Touch.
The M9 will have full integration with the main CPU courses. Now that it has moved onto the main processor, there are still a lot of questions. Chipworks' Dick James thought from the die shot that the M9 looked like it was in the same package, but not on the same die. That would make it a System In Package type solution like the Apple Watch has. If that is the case, there's a fair chance it's still an NXP design. If it's on die, I would say both possibilities should be entertained - it's a licensed NXP design or an Apple custom one integrated into the die. The CPU already manages low power states and small bursts of light activity, so that should fit right in with what the M9 wants to do.
Motorola integrated an always-on listening process first with the Moto X, and they likely had more tolerance to some small amount of current for the process because they have a bigger battery. I'm sure that moving it on chip saves them power (in addition to PCB complexity and space).
Optimizing power and other aspects of the RF chain is only going to get more popular. Analog/RF circuitry is hard to do well, so Apple has to take their time if they are working on a custom solution.
Likely 2GB. Some people seem to have picked up on this story of it having 2GB, but the detail isn't explained at all so I think it's more likely a typo. (Edit: looks like there's another, more credible source now https://www.reddit.com/r/apple/comments/3ka86y/no_mention_of_ram_in_new_iphone_or_ipad_pro/cuwb6sz)
The most likely reason I think it has 2GB, other than the rumors from reliable sources before the reveal, is actually related to the game tech demo they did on the iPhone. When they were gleefully listed the new effects they could add, the first one they mentioned was "high resolution textures." In the gaming world, high resolution textures are resources-speak for RAM intensive. If they're able to do higher resolution textures than they were before, it's likely because they have a bigger pool of RAM to play with.
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According to GSMARENA the A9 is a dual core 2Ghz, going from 20nm to 14nm and increasing 600Mhz while maintaining the same battery life. Is there some truth to it?
http://www.gsmarena.com/apple_iphone_6s_plus-7243.php
crmjenkins said:
True, but Apple did a cracking job with its ground-up reimplementation of the ARM core. Admittedly that was an almost totally different discipline of chip design and the feed-in of expertise involved the acquisition of two entire companies that I can immediately think of (PA Semi & Intrinsity) but, as you say, this RF stuff is only going to get more popular (because it can be so critical to the performance characteristics of the phone). I'm ultimately quite optimistic that Apple can do some real innovation here when the time is right, i.e. when it's happy that it's got internal solutions that are strong enough and ready to go into production.
Does anyone have any insight into the question I asked earlier re number of cores in an iPhone? It's mostly idle curiosity on my part but I suspect it's quite a few more than just the two main computing cores in the SoC. If nothing else there's presumably another for what was the M8 and then others in various radio/network chips. I also wonder how many of those are ARM based; most of them I would think.
Thanks to CHRM; attached (I hope) an annotated pic of the A9; if we assume a shrink to 80% of the SRAM block wrt the A8 (i.e. 4 MB), that gives us a die size of ~116 mm2, or 10.8 x 10.8 mm square.
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Thanks for stopping in! That scaling factor seems a bit conservative actually. That would only be 6 mm^2 short of their largest iPhone die (A5). Anandtech's piece on the Exynos 7420 suggests scaling could be as good as 60 to 70% going from 20LPE to 14LPE, so maybe 70% is a bit closer? That assumes TSMC and Samsung 20nm are roughly equivalent.
So according to Apple, the iPad pro with the A9X has a revamped memory controller that delivers much higher read/write speeds from and to the NAND. What was in the A8(X) and what do you think Apple has put in the A9X?
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Don't confuse memory (RAM) with storage (NAND), two different subsystems. No one outside of Apple knows, we have to wait for the teardown to see what they mean because this would likely be the first of its kind.
It is possible we're seeing a desktop-ish class controller with super-fast random performance like in the latest Mac models with PCIe SSD storage.
I was talking about the NAND. Should've made that clear which I will do right now.
Checked the TSMC 20nm metal pitch, also 64 nm, similar to Samsung 20LPM; if we go with shrink to 70%, that gives us a die size of 102 mm2.
Ok, so maybe not as much scaling, but 102 jives more with the package growth (package looks 10.5% bigger based on leaked PCB). Assuming proportional die growth from 89 mm^2 from A8 is around 98 mm^2.
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