What to expect from the iPhone 6S, Apple's A9, and beyond

[redman042]

The most likely reason I think it has 2GB, other than the rumors from reliable sources before the reveal, is actually related to the game tech demo they did on the iPhone. When they were gleefully listed the new effects they could add, the first one they mentioned was "high resolution textures." In the gaming world, high resolution textures are resources-speak for RAM intensive. If they're able to do higher resolution textures than they were before, it's likely because they have a bigger pool of RAM to play with.

That's a really good point.

I had latched onto 3D Touch evidence for 2GB, given that this feature was designed to provide speedy navigation, and the preview (peek) windows being opened are essentially a new form of multitasking with little user tolerance for lag. I figured they needed more headroom to make that work well. But certainly, high res game textures is a stronger pointer to more RAM.

 

[chrmjenkins]

Assuming the phone shown was a 6s,not a 6s+, the package was ~14.7 mm square.

Do you have A8 package measurements for comparison? Also I believe Samsung claimed industry leading 14nm SRAM density.

Edit: sounds like the codename for the A9 core may be "Twister." We don't know for sure how Apple's naming scheme works, but it sounds like it makes it an evolution of Cyclone and Typhoon, rather than a new name meaning a new microarchotecture.

And there's two of them. No third core or big.LITTLE scheme going as some rumors have suggested.

 

[chipworksdick]

Do you have A8 package measurements for comparison? Also I believe Samsung claimed industry leading 14nm SRAM density.

Edit: sounds like the codename for the A9 core may be "Twister." We don't know for sure how Apple's naming scheme works, but it sounds like it makes it an evolution of Cyclone and Typhoon, rather than a new name meaning a new microarchotecture.

And there's two of them. No third core or big.LITTLE scheme going as some rumors have suggested.

A8 phone package was 13.7 x 14.5 mm, so the same order of magnitude.

 

[jimbo1mcm]

OP: Start house hunting in Cupertino. Make sure you get a desk with a window.

 

[decafjava]

Excellent article. Nice to sink my teeth into after returning from a holiday.

 

[chrmjenkins]

A8 phone package was 13.7 x 14.5 mm, so the same order of magnitude.

Thanks. Sounds like our scaling factor is probably within the ballpark then.

 

[chrmjenkins]

Here's a shot of both die side by side (A8 vs. A9). Given a package estimated to be 10.5% larger, I've assumed the A9 is 10.5% larger as a scaling factor. In the image, the A8 is 505 by 624 pixels, or 315120 total pixels. The A9 is 595 by 602, or 358190 total pixels. A8 total pixels increased by 10.5% is 348207 total pixels, so we only need to scale 2.9% down for all comparisons.

(credit to iMacmatician for A9 partitioning in shot above)

With that said:
A8 SRAM: 121 x 136 = 16456 pixels
A9 SRAM: 74 x 108 (x 0.971) = 7760 pixels (x total 2) = 15520 pixels

A8 L2: 45 x 73 = 3285 (x total 2) = 6570 pixels
A9 L2: 88 x 165 (x0.971) = 14098 pixels

So, it looks as though we're looking at 4MB SRAM again on A9 (with minimal scaling from process change) and 2MB L2 cache per CPU core on A9, up from 1MB on A8 and matching 2MB per core on A8X. Of course, there are several potential sources of error including die cutouts not equal relative to edge of the chip, as well as the 10.5% growth not being representative. There's also selection error in defining the edges of the L2 (less so on the L3 SRAM). I think these quantities are sufficiently close or far apart enough to justify the above conclusions though.

 

[chrmjenkins]

Interesting that the L2 cache reports as 3MB. It does not report the SRAM as L3 cache.

https://twitter.com/MoonshineDesign/status/646168412717117440

 

[chipworksdick]

Checked the TSMC 20nm metal pitch, also 64 nm, similar to Samsung 20LPM; if we go with shrink to 70%, that gives us a die size of 102 mm2.

CORRECTION! I confused linear shrink with area shrink! Assuming ONE of the SRAM blocks is 4 MB (~4.9 mm2 in the A8), an 80% linear shrink (64% area shrink) will give us SRAM size of ~3.14 mm2, and a 70% linear shrink (area shrink to 49%) will give us ~2.4 mm2.

Guesstimating the SRAM block as a proportion of the chip area in the die shot, that gives us die sizes of ~93 mm2 or ~71 mm2 for the 80% and 70% shrinks respectively. The A8 was 89 mm2; an 80% shrink would be 57 mm2, and 70% would be 43.6 mm2, so clearly more functionality - so maybe 8 MB of L3 cache, as well as the six GPU cores instead of four in the A8.

 

[Galdom]

So when do we get an update on Apple A10 and iPhone 7?