It's well-known, from TSMC's own press releases, that the N4P process (likely used in the A16) is 5 nm, not 4 nm:
Hsinchu, Taiwan, R.O.C., Oct. 26, 2021 - TSMC (TWSE: 2330, NYSE: TSM) today introduced its N4P process, a performance-focused enhancement of the 5-nanometer technology platform.
pr.tsmc.com
"As the third major enhancement of TSMC’s
5nm family, N4P will deliver an 11% performance boost over the original N5 technology and a 6% boost over N4."
So how much weight should we give to DigiTimes' TSMC reporting when they aren't even aware of something so basic?
And why doesn't MR do some basic fact-checking before posting this stuff? Given that the whole point of this article is to report on a process change, you'd think they want to get the process descriptions right.
This doesn't make sense. First they say that
mass production on the first gen 3 nm chip (N3) starts in a few days, but now they're saying that production on 3 nm is unlikely to ramp up until the
next gen 3 nm (N3E) gets underway. This is just screaming out for clarification, yet MR gives us none. Come on guys, how putting some thought into these articles, rather than just cutting and pasting a few quotes from another source (which, incidentally is behind a paywall, preventing us from checking it ourselves)?
Oh Jesus Christ. Do you also want to tell us the breaking news that nothing on N5 is actually sized at 5nm, and nothing on N3 is sized at 3nm?
Look that ship has sailed. Anyone who hasn't been dead for the past ten years is WELL AWARE that N5 means '5nm class" which means fsckall 5nm related except that it's a set of improvements that give you about 1.8x density increase over N7.
Likewise anyone who actually matters and cares is well aware that N4 is an optical shrink of N5. You don't need to act like you're Woodward and Bernstein here revealing some scandal.
Finally the N3/N3E situation is also well understood.
- TSMC began by designing N3. The yield was disappointing and this has not improved as much as was hoped.
- Given this (and somewhat in parallel, because TSMC always has a plan B in hand) they designed a second process N3E that is not quite as dense as N3, but better in other ways (definitely better yield, slightly better power and frequency); overall a better a set of tradeoffs.
- OK, so that at this point, which process gets rolled out? Answer
+ Apparently Apple will use N3 for SOME products (probably low volume, probably those that have been in the pipeline as designed for N3 from the start, so likely the M2 Pro, Max, Ultra? Possibly also the first round of chips for glasses?) Apple will likely do this to meet schedule. But everyone, Apple and TSMC included, want to get off N3 as soon as N3E is ready.
+ OTHER COMPANIES, and Apple's main volume (ie A17, M3), will move to N3E as soon as it is available.
This all makes perfect sense, and fits with everything we know about N3 and N3E.
If you want to follow this stuff, read the people who explain it well , like Dylan Patel:
Shrinking finally costs more, Moore’s Law is now dead in economic termsA couple of weeks ago, we were able to attend IEDM, where TSMC presented many details about their N3B and N3E, 3nm class…
www.semianalysis.com
(though even Dylan can't resist becoming hysterical when it comes to Apple...)
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Going forward you need to realize that lithography is only one part of chip manufacturing, and the significant next few steps are not captured by obsessing over "5nm" vs "3nm".
What mattered was
- N7 introduced EUV
- N5 used more EUV
- N3 tried to use double-patterned EUV, but that was too ambitious and so
- N3E uses all the other improvements of N3 (eg chemical improvements) but single-pattered EUV
-N2 will use high-NA EUV which allows for smaller lithography while still not yet requiring double patterning.
- N2 will also introduce GAA FETs which are not smaller than FinFETs, but will have lower power and higher frequencies.
- HOWEVER right now the biggest limitation in designs is not transistor size, it is wiring density. Lithography can't really help with that. What's needed is to move as many wires as possible to BELOW the transistors rather than having them all above. This is so-called BSPD (back-side power delivery).
In other words the same moron crowd that have recently become hysterical about lack of SRAM density improvements for N3 need to get ready for another round of hysteria for N2 (even though this was al understood and expected years ago). N2, like N3,
- improves transistor QUALITY (power, frequency)
- allows for smaller transistor which gives improved logic density BUT
- does not allow for much density improvement where wires dominate (ie SRAM)
You can see some of the numbers here:
www.anandtech.com
BSPD is currently scheduled for a second phase of N2, an N2E or N2P or whatever it's named. For what I care about, it's a more interesting development than N2 and GAA, and I suspect that TSMC want to introduce it as soon as possible; but it is a very different sort of tech, and requires a whole lot of novel fab tooling.
Intel is in essentially the same place. The names of i4, i3 and i18 just do not matter, they're just labels (cf N4 vs N5). What matters are the concrete changes of
- use of EUV
- how many layers of EUV
- high NA EUV
- GAA
- BSPD
Each of those is a real step forward, not minor tweaks. Minor tweaks have their value (if I can get eg a 6% performance improvement for free, who's complaining!? That's why an N4 or an N3E have real value!) but it's the big steps forward that build the future.